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MC68HC05L28/D
MC68HC05L28 TECHNICAL DATA
!MOTOROLA
HC05
MC68HC05L28 MC68HC705L28
TECHNICAL DATA
!MOTOROLA
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE I2C-BUS A/D CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 A
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE I2C-BUS A/D CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705L28
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MC68HC05L28 MC68HC705L28
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
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All products are sold on Motorola's Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola's Terms & Conditions of Supply is available on request.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
(c) MOTOROLA LTD., 1998
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Conventions
Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; `u' is used to indicate an undefined state (on reset).
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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D)
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5. Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? Too little detail SECTION 1 INTRODUCTION SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS SECTION 3 MEMORY AND REGISTERS SECTION 4 INPUT/OUTPUT PORTS SECTION 5 CORE TIMER SECTION 6 16-BIT PROGRAMMABLE TIMER SECTION 7 LIQUID CRYSTAL DISPLAY DRIVER MODULE SECTION 8 I2C-BUS SECTION 9 A/D CONVERTER SECTION 10 RESETS AND INTERRUPTS SECTION 11 CPU CORE AND INSTRUCTION SET SECTION 12 ELECTRICAL SPECIFICATIONS SECTION 13 MECHANICAL DATA SECTION 14 ORDERING INFORMATION SECTION A MC68HC705L28 Comments: 6. Have you found any errors? If so, please comment: Too much detail
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REPONSE PAYEE GRANDE-BRETAGNE
Motorola Ltd., Colvilles Road, Kelvin Industrial Estate, EAST KILBRIDE, G75 8BR. GREAT BRITAIN. F.A.O. Technical Publications Manager (re: MC68HC05L28/D)
!MOTOROLA
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TABLE OF CONTENTS
Paragraph Number TITLE Page Number
1 INTRODUCTION
1.1 Features.................................................................................................................1-1 1.2 Mask options on the MC68HC05L28.....................................................................1-3 1.2.1 Option register (OPT).......................................................................................1-3
2 MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation ................................................................................................2-1 2.1.1 MC68HC05L28 modes of operation ................................................................2-2 2.1.1.1 Single chip mode........................................................................................2-2 2.1.1.2 RAM bootloader mode ...............................................................................2-2 2.1.2 MC68HC705L28 modes of operation ..............................................................2-4 2.1.2.1 EPROM bootloader mode ..........................................................................2-4 2.1.2.2 RAM bootloader mode ...............................................................................2-4 2.2 Pin descriptions .....................................................................................................2-6 2.2.1 VDD and VSS ..................................................................................................2-6 2.2.2 IRQ0 ................................................................................................................2-6 2.2.3 IRQ1.................................................................................................................2-6 2.2.4 IRQ2.................................................................................................................2-6 2.2.5 OSC1, OSC2 ...................................................................................................2-7 2.2.5.1 Crystal ........................................................................................................2-8 2.2.5.2 External clock .............................................................................................2-8 2.2.6 RESET.............................................................................................................2-8 2.2.7 PA0 - PA7, PB0 - PB7.....................................................................................2-9 2.2.8 PD0 - PD5 .......................................................................................................2-9 2.2.9 BP0 - BP3, FP0 - FP17 ..................................................................................2-9 2.2.10 AD0 - AD1, VREFH/VREFL ............................................................................2-9 2.3 Low power modes..................................................................................................2-10 2.3.1 STOP ...............................................................................................................2-10 2.3.2 WAIT ................................................................................................................2-12 2.3.3 Data retention ..................................................................................................2-12
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3 MEMORY AND REGISTERS
3.1 Registers ...............................................................................................................3-1 3.2 LCD RAM ..............................................................................................................3-1 3.3 RAM ......................................................................................................................3-1 3.4 Programming registers ..........................................................................................3-3 3.4.1 EEPROM programming register (EEPROG) ...................................................3-3 3.4.1.1 CPEN -- Charge pump enable ..................................................................3-3 3.4.1.2 ER1, ER0 -- Erase select bits ...................................................................3-3 3.4.1.3 LATCH -- EEPROM latch control ..............................................................3-4 3.4.1.4 EERC -- EEPROM RC oscillator control...................................................3-4 3.4.1.5 EEPGM -- EEPROM program control .......................................................3-4 3.4.2 EPROM programming register (PCR)..............................................................3-4 3.4.2.1 ELAT -- EPROM latch control ...................................................................3-5 3.4.2.2 PGM -- EPROM program control ..............................................................3-5
4 INPUT/OUTPUT PORTS
4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Input/output programming .....................................................................................4-1 Ports A and B ........................................................................................................4-2 Port D ....................................................................................................................4-2 Port registers .........................................................................................................4-3 Port data registers (PORTA, PORTB and PORTD) .........................................4-3 Data direction registers (DDRA, DDRB and DDRD)........................................4-3 Port D control register (COND) ........................................................................4-4 Port D select register (SELD) ..........................................................................4-4
5 CORE TIMER
5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.5 Real time interrupts (RTI) ......................................................................................5-2 Computer operating properly (COP) watchdog timer ............................................5-3 Core timer registers ...............................................................................................5-3 Core timer control and status register (CTCSR)..............................................5-3 Core timer counter register (CTCR).................................................................5-5 Core timer during WAIT .........................................................................................5-5 Core timer during STOP ........................................................................................5-5
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6 16-BIT PROGRAMMABLE TIMER
6.1 Counter ..................................................................................................................6-3 6.1.1 Counter high register Counter low register Alternate counter high register Alternate counter low register ..........................................................................6-3 6.2 Timer functions ......................................................................................................6-4 6.2.1 Timer control registers .....................................................................................6-4 6.2.1.1 Timer control register 1 (TCR1)..................................................................6-4 6.2.1.2 Timer control register 2 (TCR2)..................................................................6-6 6.2.2 Timer status register (TSR)..............................................................................6-7 6.2.3 Input capture registers .....................................................................................6-9 6.2.3.1 Input capture register 1 ..............................................................................6-9 6.2.3.2 Input capture register 2 ..............................................................................6-10 6.2.4 Output compare registers ................................................................................6-11 6.2.4.1 Output compare register 1..........................................................................6-11 6.2.4.2 Output compare register 2..........................................................................6-12 6.3 Timer during WAIT mode.......................................................................................6-13 6.4 Timer during STOP mode......................................................................................6-13 6.5 Timer state diagrams .............................................................................................6-13
7 LIQUID CRYSTAL DISPLAY DRIVER MODULE
7.1 7.2 7.3 7.4 7.5 LCD RAM ..............................................................................................................7-2 LCD operation........................................................................................................7-2 Timing signals and LCD voltage waveforms..........................................................7-3 LCD control register...............................................................................................7-8 LCD during WAIT mode.........................................................................................7-8
8 I2C-BUS
8.1 I2C-bus features.....................................................................................................8-1 8.2 I2C-bus system configuration.................................................................................8-2 8.3 I2C-bus protocol.....................................................................................................8-2 8.3.1 START signal ...................................................................................................8-2 8.3.2 Transmission of the slave address ...................................................................8-2 8.3.3 Data transfer ....................................................................................................8-4 8.3.4 STOP signal .....................................................................................................8-4 8.3.5 Repeated START signal...................................................................................8-4 8.3.6 Arbitration procedure .......................................................................................8-4
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8.3.7 Clock synchronization ......................................................................................8-5 8.3.8 Handshaking....................................................................................................8-5 8.4 Registers ...............................................................................................................8-6 8.4.1 I2C-bus address register (MADR) ....................................................................8-6 8.4.2 I2C-bus frequency divider register (FDR).........................................................8-6 8.4.3 I2C-bus control register (MCR) ........................................................................8-7 8.4.4 I2C-bus status register (MSR)..........................................................................8-8 8.4.5 I2C-bus data register (MDR) ............................................................................8-10 8.5 Programming .........................................................................................................8-10 8.5.1 Initialization ......................................................................................................8-10 8.5.2 START signal and the first byte of data............................................................8-10 8.5.3 Software response ...........................................................................................8-11 8.5.4 Generation of a STOP signal ...........................................................................8-12 8.5.5 Generation of a repeated START signal ..........................................................8-12 8.5.6 Slave mode ......................................................................................................8-13 8.5.7 Arbitration lost ..................................................................................................8-13 8.5.8 Operation during STOP and WAIT modes .......................................................8-13
9 A/D CONVERTER
9.1 A/D converter operation.........................................................................................9-1 9.2 A/D registers..........................................................................................................9-3 9.2.1 A/D status/control register (ADSTAT)...............................................................9-3 9.2.1.1 COCO -- Conversion complete flag ..........................................................9-3 9.2.1.2 ADRC -- A/D RC oscillator control ............................................................9-3 9.2.1.3 ADON -- A/D converter on ........................................................................9-3 9.2.1.4 CH3 - CH0 -- A/D channels 3, 2, 1 and 0.................................................9-4 9.2.2 A/D input register (ADIN) .................................................................................9-5 9.2.3 A/D result data register (ADDATA) ...................................................................9-5 9.3 ADx analog input ...................................................................................................9-6
10 RESETS AND INTERRUPTS
10.1 Resets .................................................................................................................10-1 10.1.1 Power-on reset...............................................................................................10-1 10.1.2 RESET pin .....................................................................................................10-1 10.1.3 Computer operating properly (COP) reset.....................................................10-2 10.2 Interrupts .............................................................................................................10-2 10.2.1 Non-maskable software interrupt (SWI).........................................................10-3 10.2.2 Maskable hardware interrupts........................................................................10-3 10.2.2.1 External interrupt (IRQ0, IRQ1, IRQ2) .....................................................10-5 10.2.2.2 Real time and core timer (CTIMER) interrupts.........................................10-7
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Programmable 16-bit timer interrupt.........................................................10-7 I2C interrupts ...........................................................................................10-8 Hardware controlled interrupt sequence ........................................................10-8
11 CPU CORE AND INSTRUCTION SET
11.1 Registers .............................................................................................................11-1 11.1.1 Accumulator (A) .............................................................................................11-1 11.1.2 Index register (X)............................................................................................11-2 11.1.3 Program counter (PC) ....................................................................................11-2 11.1.4 Stack pointer (SP) ..........................................................................................11-2 11.1.5 Condition code register (CCR).......................................................................11-2 11.2 Instruction set ......................................................................................................11-3 11.2.1 Register/memory Instructions ........................................................................11-4 11.2.2 Branch instructions ........................................................................................11-4 11.2.3 Bit manipulation instructions ..........................................................................11-4 11.2.4 Read/modify/write instructions .......................................................................11-4 11.2.5 Control instructions ........................................................................................11-4 11.2.6 Tables.............................................................................................................11-4 11.3 Addressing modes ...............................................................................................11-11 11.3.1 Inherent..........................................................................................................11-11 11.3.2 Immediate ......................................................................................................11-11 11.3.3 Direct..............................................................................................................11-11 11.3.4 Extended........................................................................................................11-12 11.3.5 Indexed, no offset...........................................................................................11-12 11.3.6 Indexed, 8-bit offset........................................................................................11-12 11.3.7 Indexed, 16-bit offset......................................................................................11-12 11.3.8 Relative ..........................................................................................................11-13 11.3.9 Bit set/clear ....................................................................................................11-13 11.3.10 Bit test and branch .........................................................................................11-13
12 ELECTRICAL SPECIFICATIONS
12.1 12.2 12.3 12.4 12.5 Maximum ratings .................................................................................................12-1 Thermal characteristics and power considerations..............................................12-2 DC electrical characteristics for 5V operation......................................................12-3 AC electrical characteristics for 5V operation ......................................................12-4 A/D converter characteristics...............................................................................12-5
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13 MECHANICAL DATA
13.1 13.2 Pin configurations -- 56-pin SDIP .......................................................................13-1 Mechanical dimensions -- 56-pin plastic shrink dual-in-line (SDIP) ...................13-2
14 ORDERING INFORMATION
14.1 14.2 14.3 EPROM ...............................................................................................................14-1 Verification media ................................................................................................14-1 ROM verification units (RVU)...............................................................................14-2
A MC68HC705L28
A.1 A.2 A.2.1 A.2.2 A.2.3 A.3 A.4 A.4.1 A.4.2 A.5 A.6 Features ............................................................................................................... A-1 Modes of operation............................................................................................... A-1 Single chip mode ............................................................................................ A-2 EPROM bootloader mode............................................................................... A-2 RAM bootloader mode.................................................................................... A-4 VPP ...................................................................................................................... A-4 EPROM programming register (PCR) .................................................................. A-5 ELAT -- EPROM latch control ........................................................................ A-5 PGM -- EPROM program control................................................................... A-5 Pin configurations -- 56-pin SDIP ........................................................................ A-6 Ordering information............................................................................................. A-6
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TABLE OF CONTENTS
MC68HC05L28
LIST OF FIGURES
Figure Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 5-1 6-1 6-2 6-3 6-4 6-5 7-1 7-2 7-3 7-4 7-5 7-6 8-1 8-2 8-3 9-1 9-2 10-1 11-1 11-2 12-1 13-1 13-2 A-1 A-2 TITLE Page Number
MC68HC05L28/MC68HC705L28 block diagram....................................................1-2 RAM bootloader circuit ...........................................................................................2-3 MC68HC705L28 EPROM programming circuit ......................................................2-5 Oscillator connections ............................................................................................2-7 RC connection for external POR ............................................................................2-8 STOP flowchart ......................................................................................................2-11 WAIT flowchart .......................................................................................................2-13 Memory map of the MC68HC05L28 and MC68HC705L28....................................3-2 Standard I/O port structure.....................................................................................4-2 Core timer block diagram........................................................................................5-1 16-bit programmable timer block diagram ..............................................................6-2 Timer state timing diagram for reset .......................................................................6-14 Timer state timing diagram for input capture ..........................................................6-14 Timer state timing diagram for output compare ......................................................6-15 Timer state timing diagram for timer overflow.........................................................6-15 LCD system block diagram.....................................................................................7-1 Voltage level selection ............................................................................................7-3 LCD waveform with 2 backplanes, 1/2 bias ............................................................7-4 LCD waveform with 2 backplanes, 1/3 bias ............................................................7-5 LCD waveform with 3 backplanes ..........................................................................7-6 LCD waveform with 4 backplanes ..........................................................................7-7 I2C bus transmission signal diagrams ....................................................................8-3 Clock synchronization.............................................................................................8-5 Example of a typical I2C-bus interrupt routine ........................................................8-14 A/D converter block diagram ..................................................................................9-2 Electrical model of an A/D input pin........................................................................9-6 Interrupt flow chart................................................................................................10-4 Programming model .............................................................................................11-1 Stacking order ......................................................................................................11-2 Equivalent test load ..............................................................................................12-2 56-pin SDIP pinout for the MC68HC05L28/MC68HC705L28...............................13-1 Mechanical dimensions for 56-pin SDIP...............................................................13-2 MC68HC705L28 EPROM programming circuit ..................................................... A-3 56-pin SDIP pinout for the MC68HC705L28 ......................................................... A-6
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LIST OF FIGURES
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LIST OF TABLES
Table Number 2-1 2-2 2-3 2-4 3-1 3-2 4-1 4-2 5-1 5-2 7-1 7-2 8-1 9-1 9-2 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 12-1 12-2 12-3 12-4 12-5 14-1 A-1 A-2 A-3 TITLE Page Number
MC68HC05L28 operating mode entry conditions ..................................................2-1 MC68HC705L28 operating mode entry conditions ................................................2-1 RAM bootloader mode jump vector (MC68HC05L28)............................................2-3 RAM bootloader mode jump vectors (MC68HC705L28) ........................................2-3 Erase mode select..................................................................................................3-3 Register outline.......................................................................................................3-6 I/O pin states ..........................................................................................................4-1 I/O configuration functions......................................................................................4-4 Minimum COP reset times......................................................................................5-3 Example RTI periods ..............................................................................................5-4 LCD RAM organization...........................................................................................7-2 Multiplex ratio/backplane selection .........................................................................7-8 I2C-bus prescaler....................................................................................................8-7 A/D clock selection .................................................................................................9-4 A/D channel assignment.........................................................................................9-4 Interrupt priorities .................................................................................................10-3 IRQ1 interrupt sensitivity ......................................................................................10-6 IRQ2 interrupt sensitivity ......................................................................................10-7 MUL instruction.....................................................................................................11-5 Register/memory instructions...............................................................................11-5 Branch instructions ...............................................................................................11-6 Bit manipulation instructions.................................................................................11-6 Read/modify/write instructions .............................................................................11-7 Control instructions...............................................................................................11-7 Instruction set .......................................................................................................11-8 M68HC05 opcode map.........................................................................................11-10 Maximum ratings ..................................................................................................12-1 Package thermal characteristics...........................................................................12-2 DC electrical characteristics .................................................................................12-3 Control timing .......................................................................................................12-4 A/D converter characteristics................................................................................12-5 MC order numbers................................................................................................14-1 MC68HC705L28 operating mode entry conditions ............................................... A-1 MC68HC705L28 bootloader mode jump vectors .................................................. A-4 MC68HC705L28 order numbers ........................................................................... A-6
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LIST OF TABLES
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MC68HC05L28
1
1
INTRODUCTION
The MC68HC05L28 is a flexible general-purpose microcomputer, particularly suited to applications throughout the consumer and automotive industries. It is a member of the highly successful Motorola M68HC05 family of microcomputers and includes many of the standard features of this family. Its hardware includes 8K of ROM, 240 bytes of EEPROM and 256 bytes of RAM, plus a multi-master I2C interface, an A/D converter and an LCD driver subsystem. The LCD subsystem is particularly flexible and can be programmed to drive a wide range of industry-standard LCD devices -- making the MC68HC05L28 particularly suited to many applications in radio, TV and compact disc systems. The MC68HC05L28's communications, A/D and LCD modules and its two timer modules provide the perfect combination for car dashboard applications, where analog signals from speed and distance sensors have to be converted to digital signals before being processed and displayed. The MC68HC705L28 is an EPROM equivalent version of the MC68HC05L28, with 8K of EPROM instead of 8K of ROM. All references to the MC68HC05L28 apply equally to the MC68HC705L28, unless otherwise noted. References specific to the MC68HC705L28 are italicized in the text and also, for quick reference, they are summarised in Appendix A.
1.1
* * * * * *
Features
Fully static chip design featuring the industry standard M68HC05 core Multi-master I2C-bus communication port 8176 bytes of user ROM (MC68HC05L28); 8128 bytes of user EPROM (MC68HC705L28) 240 bytes of EEPROM 240 bytes of bootstrap ROM 256 bytes of RAM
I2C-bus is a proprietary Philips interface bus
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MC68HC05L28
INTRODUCTION
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1
* * * * * * * * LCD subsystem with 18 frontplanes and 4 backplanes 16-bit programmable timer with 2 input capture and 2 output compare functions 15-stage, multifunctional core timer, with overflow, real-time interrupt and computer operating properly (COP) watchdog timer (software selectable) 3 interrupt request pins with edge or edge-and-level sensitive triggering (software selectable) 2-channel, 8-bit analog-to-digital converter 16 dedicated I/O lines 6 I/O lines shared with the 16-bit programmable timer and the multi-master I2C-bus interface Power saving STOP and WAIT modes Available in 56-pin SDIP package
256 x 8 RAM
8176 x 8 user ROM or 8128 x 8 user EPROM
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PD5 PD4
OSC1 OSC2
Oscillator
240 x 8 bootstrap ROM Port B 240 x 8 EEPROM
SCL0 SDA0 TCMP2
Core timer COP system
IRQ0 IRQ1 IRQ2
Port D
RESET
I2C
Port A
M68HC05 CPU
16-bit TCAP2 timer TCMP1
TCAP1
PD3 PD2 PD1 PD0
VDD VSS
8-bit, 2-channel A/D converter
AD1 AD0 VREFL VREFH BP0 BP1 BP2 BP3
18 x 4 LCD subsystem
Figure 1-1 MC68HC05L28/MC68HC705L28 block diagram
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FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17
INTRODUCTION
MC68HC05L28
1
1.2 Mask options on the MC68HC05L28
There is only one mask option on the MC68HC05L28. This is to enable or disable the STOP instruction. It is programmed during manufacture and must be specified on the order form.
1.2.1
Option register (OPT)
In addition to its mask option, the MC68HC05L28 also has two functions that are programmable via an options register (OPT). This register can be written to once after a reset, but it can be read at any time.
Address Option register (OPT) $001D bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
IRQED COPON ???? ?100
IRQED -- IRQ edge sensitivity This bit selects the IRQ0 sensitivity. 1 (set) - The IRQ0 is edge-sensitive. The IRQ0 is edge-and-level-sensitive.
0 (clear) - Reset clears this bit.
COPON -- COP function enable/disable 1 (set) - This bit enables the COP watchdog. This bit disables the operation of the COP.
0 (clear) - Reset clears this bit.
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2
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1 Modes of operation
The MC68HC05L28 has two modes of operation available to the user - single chip and RAM bootloader. The MC68HC705L28 also has two modes of operation - single chip and EPROM/RAM bootloader. Table 2-1 and Table 2-2 show the conditions required to enter each mode on the rising edge of RESET. Table 2-1 MC68HC05L28 operating mode entry conditions
IRQ0/VPP V SS to VDD 2 x VDD 2 x VDD PB2 x 1 1 PB3 x 0 1 PB6 x V DD V DD Mode Single chip RAM bootloader Jump to RAM ($81) Load/execute RAM
Table 2-2 MC68HC705L28 operating mode entry conditions
IRQ0/VPP V SS to VDD 2 x VDD 2 x VDD 2 x VDD 2 x VDD PB2 x 0 0 1 1 PB3 x 0 1 0 1 PB6 x V DD V DD V DD V DD Mode Single chip EPROM bootloader RAM bootloader Verify only Program/verify Jump to RAM ($81) Load/execute RAM
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-1
2.1.1
MC68HC05L28 modes of operation Single chip mode
2
2.1.1.1
This is the normal operating mode of the MC68HC05L28 and the MC68HC705L28. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including two 8-bit I/O ports and one 6-bit I/O port, available to the user. All address and data activity occurs within the MCU. Single chip mode is entered on the rising edge of RESET if the voltage level on the IRQ0 pin is within the normal operating range.
Warning: In the MC68HC705L28, all vectors are fetched from EPROM in single chip mode; therefore, the EPROM must be programmed (via the bootloader mode) before the device is powered up in single chip mode.
2.1.1.2
RAM bootloader mode
The RAM bootloader mode for the MC68HC05L28 and MC68HC705L28 allows the user to perform simple load and execute instructions in RAM. To make use of this feature a circuit board should be constructed as shown in Figure 2-1. Correct configuration of port pins PB2 and PB3 enables loading of a user program into RAM for execution. The RAM bootloader is selected when the device is put into bootloader mode with PB2 held high. If PB3 is low, the program counter is set to $0081 and a previously loaded RAM program can be executed. If PB3 is high at reset a program is serially loaded from PA0 into the RAM and executed from $0081. The first byte to be loaded is the count byte which should hold the program length plus the count byte. Therefore, for a program length of $30, the count should equal $31. The maximum program size, including the count byte is 254 bytes ($FE), as two bytes must be left for the stack during download. The format of data for the RAM bootloader mode is 9600 baud, 8-bit, no parity, 1 start, 1stop (for 2 MHz bus speed). In the RAM bootloader mode interrupt vectors are mapped to pseudo-vectors in RAM (for MC68HC05L28 vectors see Table 2-4 and for MC68HC705L28 vectors seeTable 2-4). This allows programmers to use their own service-routine addresses. Each pseudo-vector is allowed three bytes of space, rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service-routine address.
TPG
MOTOROLA 2-2
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
2 x V DD
10 M 4.0 MHz
IRQ/VPP OSC1 PA0
2
RxD
V DD
OSC2 PB6 PB2
22pF
22pF
V DD
VDD
PB3
100nF 100nF
RESET
VSS
MC68HC05L28 All resistors are 10 k unless specified otherwise
PB3 Function 0 Jump to RAM ($81) 1 Load/Execute RAM
Figure 2-1 RAM bootloader circuit
Table 2-3 RAM bootloader mode jump vector (MC68HC05L28)
Address Pseudo-vector 0084 Software interrupt
Table 2-4 RAM bootloader mode jump vectors (MC68HC705L28)
Address 0083 0086 0089 008C 008F Pseudo-vector Software interrupt IRQ Core timer I 2C-bus Programmable timer
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-3
2.1.2
MC68HC705L28 modes of operation EPROM bootloader mode
2
2.1.2.1
This mode is used for programming the on-board EPROM. In bootloader mode the operation of the device is the same as in single chip mode, except that the vectors are fetched from a reserved area of ROM at locations $3FE4 to $3FEF, instead of the EPROM. The pin assignments are identical to that of single chip mode shown earlier. A recommended programming circuit is shown in Figure 2-2. Because the addresses in the MC68HC705L28 and the EPROM containing the user code are incremented independently, it is essential that the data layout in the 27128 EPROM conforms exactly to the MC68HC705L28 memory map. The bootloader uses an external 14-bit counter to address the memory device containing the code to be copied. This counter requires a clock and a reset function which are provided by the MC68HC705L28. In this mode all interrupt vectors are mapped to pseudo-vectors in RAM (see Table 2-4). This allows programmers to use their own service routine addresses. Each pseudo-vector is allowed three bytes of space, rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service routine address. The bootloader code deals with the copying of user code from an external EPROM into the on-chip EPROM. The bootloader function can only be used with an external EPROM. The bootloader performs a programming pass followed by a verify pass. Pins PB2 and PB3 are used to select various bootloader functions, including the programming mode (see Figure 2-2). Two other pins, PB1 and PB6 are used to drive the PROG and VERF LED outputs. While the EPROM is being programmed the PROG LED lights up; when programming is complete the internal EPROM contents are compared to that of the external EPROM and, if they match exactly, the VERF LED lights up. When finished programming, the PROG LEG turns off. If the MC68HC705L28 memory contents are the same as the EPROM the VERF LED lights up, otherwise no LEDs are turned on. Note: The EPROM must be erased before performing a program cycle.
2.1.2.2
RAM bootloader mode
See Section 2.1.1.2.
TPG
MOTOROLA 2-4
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
2
L1 = VERIFY L2 = PROGRAM S1 1 0 +5V
L1
S2 0 0
Function Program/verify Verify only
+5V
L2
+5V +5V
10K 10K
470
470
PB6
PB1
PB7 PB5
clock clear
+5V
+5V RESET
10K 10K S3
+5V
VDD TCAP1 TCAP2 VREFH
+5V +5V VCC VPP PGM
PB2
S2
RST Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
CLK
MC68HC705L28
PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D0 D1 D2 D3 D4 D5 D6 D7
MCM 27128 (16K EPR OM)
S1
VREFL ADIN
VPP
IRQ0/VPP OE VSS OCS1 OCS2 VSS CE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
VDD
MC74HC393 VSS
10 M 4 MHz 22pF 22pF
Figure 2-2 MC68HC705L28 EPROM programming circuit
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-5
2.2
Pin descriptions
2
Pin assignments are shown in Section 13.
2.2.1
VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground. It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply bypassing at the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
2.2.2
IRQ0
This interrupt has a software option which offers two types of interrupt triggering sensitivity. It contains an internal Schmitt trigger as part of its input to improve noise immunity.
2.2.3
IRQ1
This interrupt has a software option which offers four types of interrupt triggering sensitivity. It contains an internal Schmitt trigger as part of its input to improve noise immunity. This interrupt can be enabled/disabled independently.
2.2.4
IRQ2
This interrupt has a software option which offers four types of interrupt triggering sensitivity. It contains an internal Schmitt trigger as part of its input to improve noise immunity. This interrupt can be enabled/disabled independently.
TPG
MOTOROLA 2-6
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
2.2.5
OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal connected to these pins supplies the oscillator clock. The oscillator frequency (fOSC) is divided by two to give the internal bus frequency (fOP).
2
L OSC1
C1
RS OSC2
MCU C0 OSC1 RP (b) Crystal equivalent circuit OSC2
C OSC1
C OSC2 MCU OSC1 OSC2
(a) Crystal oscillator connections External Clock NC
(c) External clock source connections
R S (max) C0 C1 C OSC1 C OSC2 RP Q
Crystal 2MHz 4MHz 400 75 5 7 8 12 15 - 40 15 - 30 15 - 30 15 - 25 10 10 30 000 40 000
Unit pF nF pF pF M --
(d) Crystal parameters
Figure 2-3 Oscillator connections
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-7
2.2.5.1
Crystal
2
The circuit shown in Figure 2-3(a) is recommended when using a crystal . Figure 2-3(d) lists the recommended capacitance and feedback resistance values. The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified for fOSC (see Section 12.4). Use of an external CMOS oscillator is recommended when crystals outside the specified ranges are to be used. The crystal and associated components should be mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. The manufacturer of the particular crystal being considered should be consulted for specific information.
2.2.5.2
External clock
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as shown in Figure 2-3(c). The tOXOV specification (see Section 12.4) does not apply when using an external clock input. The equivalent specification of the external clock source should be used in lieu of tOXOV.
2.2.6
RESET
This active low input pin is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. This input has an internal Schmitt trigger to improve noise immunity. The MCU has its own internal power-on reset (POR) circuit. If, however, the user requires an additional POR, then an RC network can be connected to this pin as shown in Figure 2-4. The user must ensure that the RC time constant of this network is greater than the the oscillator stabilization period. A time constant of at least 100 ms is recommended.
VDD R
MC68HC05L28
RESET
C VSS
Figure 2-4 RC connection for external POR
TPG
MOTOROLA 2-8
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
2.2.7
PA0 - PA7, PB0 - PB7
These 16 I/O lines comprise ports A and B. The state of any pin is software programmable, and all the pins are configured as inputs during power-on or reset. Port B pins in output mode can sink 10mA of current to drive the LEDs.
2
2.2.8
PD0 - PD5
These six I/O lines comprise port D. The state of any pin is software programmable, and all the pins are configured as inputs during power-on or reset. This port shares its pins with the 16-bit timer and I2C subsystems. There are four read/write registers associated with the port to select the different functions. All the port bits can be configured as input/output pins or used by other systems within the MCU. This 6-bit I/O port shares its pins with other subsystems on the MCU and is controlled using the port D control (COND) and select (SELD) registers. On reset, all registers except the data register are cleared thereby configuring all port pins as normal inputs with pull-up resistors. Writing a `1' to any bit in COND connects the subsystem function to the corresponding port D pin.
2.2.9
BP0 - BP3, FP0 - FP17
These signals comprise the LCD driver subsystem. The subsystem has a maximum of 18 frontplanes and four backplanes.
2.2.10 AD0 - AD1, VREFH/VREFL
These 4 signals comprise the A-to-D interface. The subsystem has a maximum of two A/D channels.
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-9
2.3
Low power modes
2
2.3.1 STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog timer) operation. During the STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits (CTOFE and RTIE) in the CTCSR are cleared by internal hardware. This removes any pending timer interrupt requests and disables any further timer interrupts. The timer prescaler is also cleared. The I-bit in the CCR is cleared to enable external interrupts. All other registers, the remaining bits in the CTCSR, and memory contents remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an external interrupt or a reset (see Figure 2-5). The STOP instruction can be disabled by a mask option. When disabled, it is executed as a NOP.
TPG
MOTOROLA 2-10
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
STOP
2
Stop oscillator and all clocks Clear I-bit
No
Reset
Yes No External interrupt (IRQ0,1,2) Yes
Turn on oscillator Wait for time delay to stabilize
1. Fetch reset vector or 2. Service interrupt: a. stack b. set I-bit c. vector to interrupt routine
Figure 2-5 STOP flowchart
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-11
2.3.2
WAIT
2
The WAIT instruction places the MCU in a low power consumption mode, but the WAIT mode consumes more power than the STOP mode. All CPU action is suspended, but the core timer, 16-bit timer and I2C remains active. An interrupt from the core timer, 16-bit timer or I2C (if enabled) will cause the MCU to exit WAIT mode. During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory and input/output lines remain in their previous state. The core timer may be enabled to allow a periodic exit from the WAIT mode (see Figure 2-6).
2.3.3
Data retention
The contents of the RAM are retained at supply voltages as low as 2.0Vdc. This is called the data retention mode, in which data is maintained but the device is not guaranteed to operate. For lowest power consumption in data retention mode the device should be put into STOP mode before reducing the supply voltage, to ensure that all the clocks are stopped. If the device is not in STOP mode then it is recommended that RESET be held low while the power supply is outside the normal operating range, to ensure that processing is suspended in an orderly manner. Recovery from data retention mode, after the power supply has been restored, is by pulling the RESET line high. To put the MCU into data retention mode: * * Set RESET pin to zero Reduce the voltage on VDD. RESET must remain low during data retention mode
To take the MCU out of data retention: * * Return VDD to normal operating level Return RESET to logical one.
TPG
MOTOROLA 2-12
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
WAIT
2
Oscillator active Timer clock active Processor clocks stopped
No Reset
External interrupt (IRQ0,1,2) Yes
No
Yes
Restart processor clock
Yes
CTimer internal interrupt
No
1. Fetch reset vector or 2. Service interrupt: a. stack b. set I-bit c. vector to interrupt routine
Figure 2-6 WAIT flowchart
TPG
MC68HC05L28
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA 2-13
2
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 2-14
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
3
MEMORY AND REGISTERS
The MC68HC05L28 has a 16K byte memory map consisting of registers, user ROM, user RAM, bootstrap ROM, LCD RAM, EEPROM and I/O, as shown in Figure 3-1.
3
3.1
Registers
All the I/O, control and status registers of the MC68HC05L28 are contained within the first 64-byte block of the memory map (address $0000 to $003F).
3.2
LCD RAM
The 12 bytes of LCD RAM are located at address $0040 to $004B. This RAM is used to store the data needed for the LCD. See Section 7.1 for further details of the organization of these bits.
3.3
RAM
The user RAM consists of 256 bytes of memory, from $0080 to $017F. This is shared with a 64 byte stack area. The stack begins at $00FF and counts down to $00C0.
Note:
Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call.
TPG
MC68HC05L28
MEMORY AND REGISTERS
MOTOROLA 3-1
Registers
$0000 I/O (64 bytes) LCD RAM (12 bytes) $004C $0080 $00C0 $00FF $0180 $0300 EEPROM (240 bytes) $03F0 Reserved $1000 User ROM (8176 bytes) User EPROM (8128bytes) $2FC0/$2FF0 Reserved $3F00 Bootstrap ROM (240 bytes) & bootstrap vectors User vectors (16 bytes) $3FFF Stack RAM (256 bytes) Reserved
Port A data (PORTA) Port A data (PORTA) Reserved Reserved Port A data direction (DDRA) Port B data direction (DDRB) Reserved Reserved Core timer control & status (CTCSR) Core timer counter (CTCR) IRQ1 IRQ2 Reserved I2C address (MADR) I2C frequency divider (MFDR) I2C control (MBCR) I2C status (MBSR) I2C data (MDR) A/D status/control (ADSTAT) A/D Input (ADIN) A/D data (ADDATA) Reserved EEPROM program (EEPROG) EPROM program (PCR) Option (OPT) LCD control (LCD) Reserved Input capture 1 high(IC1H) Input capture 1 low (IC1L) Output compare 1 high (OC1H) Output compare 1 low (OC1L) Input capture 2 high (IC2H) Input capture 2 low (IC2L) Output compare 2 high (OC2H) Output compare 2 low (OC2L) Timer counter high (TCH) Timer counter low (TCL) Alternate counter high (ACH) Alternate counter low (ACL) Timer control 1 (TCR1) Timer control 2(TCR2) Timer status (TSR) Reserved Port D data (PORTD) Port D Data direction (DDRD) Port D control (COND) Port D select (SELD) Reserved $3F $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0F $10 $11 $12 $13 $14 $15 $16 $17 $18
$0040
3
Reserved
$3FF0
Figure 3-1 Memory map of the MC68HC05L28 and MC68HC705L28
TPG
MOTOROLA 3-2
MEMORY AND REGISTERS
MC68HC05L28
3.4 3.4.1
Programming registers EEPROM programming register (EEPROG)
Address bit 7 bit 6 CPEN bit 5 0 bit 4 ER1 bit 3 bit 2 bit 1 bit 0 State on reset
3
EEPROM program (EEPROG)
$001B
ER0 LATCH EERC EEPGM ?000 0000
3.4.1.1
CPEN -- Charge pump enable
This bit enables the charge pump which produces the internal programming voltage. It is set with the LATCH bit and should be disabled when not in use. The programming voltage is not available until EEPGM is set. 1 (set) - Charge pump is enabled. Charge pump is disabled.
0 (clear) -
3.4.1.2
ER1, ER0 -- Erase select bits
ER1 and ER0 are used to select either single byte programming or one of three erase modes: byte, block or bulk. Table 3-1 shows the modes selected for each bit configuration. These bits are readable and writeable and are cleared by reset.
Table 3-1 Erase mode select
ER1 0 0 1 1 ER0 0 1 0 1 Mode Program Byte erase Block erase Bulk erase
- -
In byte erase mode only the selected byte is erased. In block erase mode a 64-byte block of EEPROM is erased. The EEPROM memory space is divided into four 64-byte blocks ($0300-$033F, $0340-$037F, $0380-$03BF, $03C0-$03EF) and an erase to any address within a block erases that block. In bulk erase mode the entire 240 bytes of EEPROM are erased.
-
TPG
MC68HC05L28
MEMORY AND REGISTERS
MOTOROLA 3-3
3.4.1.3
1 (set)
LATCH -- EEPROM latch control
- The EEPROM address and data buses are configured for programming. This causes the address and data buses to be latched when a write to EEPROM is carried out. EEPROM cannot be read if LATCH = 1. The EEPROM address and data buses are configured for normal reads.
3
0 (clear) -
3.4.1.4
1 (set)
EERC -- EEPROM RC oscillator control
- The EEPROM uses an internal RC oscillator instead of the CPU clock. After setting, wait for time tRCON to allow the RC oscillator to stabilize. It should be set by the user when the internal bus frequency falls below 1.5 MHz. The EEPROM uses the CPU clock.
0 (clear) -
3.4.1.5
1 (set)
EEPGM -- EEPROM program control
- Programming power is connected to the EEPROM array. EEPGM can only be set if LATCH is set and is automatically cleared when LATCH = 0. Programming power is disconnected from the EEPROM array.
0 (clear) -
Note:
LATCH and EEPGM cannot be set on the same write operation
3.4.2
EPROM programming register (PCR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ELAT bit 0 State on reset
EPROM program (PCR)
$001C
PGM uuuu uu00
TPG
MOTOROLA 3-4
MEMORY AND REGISTERS
MC68HC05L28
3.4.2.1
1 (set)
ELAT -- EPROM latch control
- When this bit is set to 1, the EPROM address and data buses are configured for programming. This causes the address and data buses to be latched when a write to EPROM is executed. The EPROM cannot be read if it is set to 1. The EPROM address and data buses are configured for normal reads.
3
0 (clear) -
3.4.2.2
1 (set)
PGM -- EPROM program control
- Programming power is connected to the EPROM array. The PGM can only be set if ELAT is set and it is automatically cleared when ELAT = 0. EPROM address and data bus are configured for normal reads.
0 (clear) - Note:
ELAT and PGM cannot be set in the same write operation.
Take the following steps to program a byte of EPROM: - Apply the programming voltage VPP to the VPP pin. - Set the ELAT bit. - Write to the EPROM address. - Set the PGM bit for a time tPROG to apply the programming voltage. - Clear the ELAT and PGM bits. Note: The erased state of the EPROM is $00.
TPG
MC68HC05L28
MEMORY AND REGISTERS
MOTOROLA 3-5
Table 3-2 Register outline
State on Reset
unaffected unaffected
Register Name
Address bit 7
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 MEN MCF ADR7 CTOF
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
Port A data (PORTA) Port B data (PORTB) Reserved Reserved Port A data direction (DDRA) Port B data direction (DDRB) Reserved Reserved Core timer control/status (CTCSR) Core timer counter (CTCR) IRQ1 IRQ2 Reserved Reserved Reserved Reserved I2C address (MADR) I2C frequency divide (FDR) I2C control (MCR) I2C status (MSR) I2C data (MDR) A/D status control (ADSTAT) A/D input (ADIN) A/D data (ADDATA) Reserved Reserved Reserved EEPROM program (EEPROG) EPROM program (PCR) Option (OPT) LCD control (LCD) Reserved Input capture 1 high (IC1H) Input capture 1 low(IC1L) Output compare 1 high(OC1H) Output compare 1 low (OC1L) Input capture 2 high (IC2H) Input capture 2 low (IC2L) Output compare 2 high (OC2H) Output compare 2 low (OC2L)
(1)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0000 0000
RTIF
CTOFE
RTIE
RT1
RT0
0000 0011 0000 0000
IRQ1INT IRQ1ENA IRQ1LV IRQ1EDGIRQ1RSTIRQ1VAL ??00 000? IRQ2INT IRQ2ENA IRQ2LV IRQ2EDGIRQ2RSTIRQ2VAL ??00 000? unaffected unaffected unaffected unaffected ADR6 ADR5 ADR4 MBC4 MIEN MAAS MSTA MBB MTX MAL ADR3 MBC3 TXAK ADR2 MBC2 MMUX SRW MIF RXAK ADR1 MBC1 MBC0 0000 000? ???0 0000 0000 00?? 1000 ?001 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu
TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 COCO ADRC ADON CH3 CH2 CH1 AD1 CH0 AD0
CPEN
ER1
ER0
LATCH
EERC EEPGM ?000 0000 ELAT PGM uuuu uu00
IRQED COPON ???? ?100 VLCDON FDISP MUX4 MUX3 DISON ?000 0000
uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TPG
MOTOROLA 3-6
MEMORY AND REGISTERS
MC68HC05L28
Table 3-2 Register outline
State on Reset
1111 1111 1111 1100 1111 1111 1111 0011 IC1IE IC2IE OC1IE OC2IE IC1F IC2F OC1F TOF TOIE CO1E CO2E TCAP1 TCAP2 OC2F IEDG1 IEDG2 OLV1 OLV2 0000 0uu0 0000 0000 uuuu 11u0
Register Name
Timer counter high (TCH) Timer counter low (TCL) Alternate counter high (ACH) Alternate counter low (ACL) Timer control 1 (TCR1) Timer control 2 (TCR2) Timer status (TSR) Reserved Port D data (PORTD) Port D data direction (DDRD) Port D control (COND) Port D select (SELD) Reserved (1) MC68HC705L28 only
Address bit 7
$0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 $34-$3F
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
3
unaffected DDRD5 DDRD4 DDRD3 DDRDD2 DDR1 DDRD0 ??00 0000 COND5 COND4 COND3 COND2 COND1 COND0 ??00 0000 PD5/ SCL0 PD4/ SDA0 PD3/ TCMP2 PD2/ TCAP2 PD1/ PD0/ TCMP1 TCAP1 ??00 0000
TPG
MC68HC05L28
MEMORY AND REGISTERS
MOTOROLA 3-7
3
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 3-8
MEMORY AND REGISTERS
MC68HC05L28
4
INPUT/OUTPUT PORTS
In single chip mode, the MC68HC05L28 has a total of 22 I/O lines, arranged as two 8-bit ports (A and B) and one 6-bit port (D). Each I/O line is individually programmable as either input or output, under the software control of the data direction registers. Port D shares various I/O configurations with the timer and I2C subsystems. To avoid glitches on the output pins, data should be written to the I/O port data register before writing ones to the corresponding data direction register bits to set the pins to output mode.
4
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The direction of each pin is normally determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any standard I/O port pin is configured as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding DDR bit is cleared. At power-on or reset, all DDRs are cleared, configuring all port pins as inputs. The data direction registers can be written to or read by the MCU. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. The operation of the standard port hardware is shown schematically in Figure 4-1. This is summarized in Table 4-1, which shows the effect of reading from or writing to an I/O pin in various circumstances. Note that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states
R/W 0 0 1 1 DDRn 0 1 0 1 Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch, and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read.
TPG
MC68HC05L28
INPUT/OUTPUT PORTS
MOTOROLA 4-1
M68HC05 Inter nal Connections
Data direction register bit
DDRn
Latched data register bit
Data
Output buffer
I/O pin
4
O/P data buffer Input buffer
DDRn 1 Output 1 0 Input 0

DATA 0 1 0 1
I/O Pin 0 1 tristate tristate
Figure 4-1 Standard I/O port structure
4.2
Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a data direction register. Reset does not affect the state of the data register, but clears the data direction register, thereby returning all port pins to input mode. Writing a `1' to any DDR bit sets the corresponding port pin to output mode.
4.3
Port D
Port D is a 6-bit non-standard port which shares its pins with the timer and I2C subsystems. There are four read/write registers associated with the port for defining the different functions. All the port D pins can be configured as input/output pins or can be used by other subsystems within the MCU. Setting bits 5-0 in the port D select register to logical `1' configures the pin as dedicated to the timer or I2C subsystems. For details of the alternative function of each port D pin see Section 2.2.8.
4.4
Port registers
The following sections explain in detail the individual bits in the data and control registers associated with the ports.
TPG
MOTOROLA 4-2
INPUT/OUTPUT PORTS
MC68HC05L28
4.4.1
Port data registers (PORTA, PORTB and PORTD)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Unaffected Unaffected Unaffected
Port A data (PORTA) Port B data (PORTB) Port D data (PORTD)
$0000 $0001 $0030
Each bit can be configured as input or output via the corresponding data direction bit in the port data direction register (DDRx). Reset does not affect the state of the port data registers. Each of the port D bits is shared with another MCU subsystem. The configuration of this register is determined by the setting of individual bits in the port D control register. See Section 4.4.3.
4
4.4.2
Data direction registers (DDRA, DDRB and DDRD)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000 0000 0000 0000 0000
Port A data direction (DDRA) Port B data direction (DDRB) Port D data direction (DDRD)
$0004 $0005 $0031
Writing a `1' to any bit configures the corresponding port pin as an output; conversely, writing any bit to `0' configures the corresponding port pin as an input. Reset clears these registers, thus configuring all ports as inputs.
4.4.3
Port D control register (COND)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
Port D control (COND)
$0032
The select register, data direction register and control register determine the function of the I/O port, as shown in Table 4-2.
TPG
MC68HC05L28
INPUT/OUTPUT PORTS
MOTOROLA 4-3
Table 4-2 I/O configuration functions
DDRD 0 0 1 1 COND 0 1 0 1 Function Input with pull-up Input without pull-up Push-pull output Open-drain output without pull-up
4
4.4.4
Port D select register (SELD)
Address bit 7 bit 6 bit 5 PD5/ SCL0 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
Port D select (SELD)
$0033
PD4/ PD3/ PD2/ PD1/ PD0/ 0000 0000 SDA0 TCMP2 TCAP2 TCMP1 TCAP1
Setting bits 5-0 in the port D select register to logical `1' configures the pin to be dedicated to the timer or the I2C bus subsystems. This select bit overrides the effect that the DDR register has on the port direction. The user must ensure that the DDR and COND register bits are programmed correctly to obtain the desired pin configuration. PD5/SCL0 -- Port D pin 5/SCL0 select 1 (set) - This pin is configured as the I2C clock and is always an open-drain I/O. If a pull-up is required then bit 5 in the DDRD and COND registers must be cleared. This pin is configured as I/O pin PD5.
0 (clear) -
PD4/SDA0 -- Port D pin 4/SCL1 select 1 (set) - This pin is configured as the I2C data pin and is always an open-drain I/O. If a pull-up is required then bit 4 in the DDRD and COND registers must be cleared. This pin is configured as I/O pin PD4.
0 (clear) -
PD3/TCMP2 -- Port D pin 3/TCMP2 select 1 (set) - This pin is configured as timer output compare 2 output. Setting bit 3 in the COND register makes it an open drain output This pin is configured as I/O pin PD3.
0 (clear) -
TPG
MOTOROLA 4-4
INPUT/OUTPUT PORTS
MC68HC05L28
PD2/TCAP2 -- Port D pin 2/TCAP2 select 1 (set) - This pin is configured as timer input capture 2 input. Clearing bit 2 in the COND register enables the pull-up resistor. This pin is configured as I/O pin PD2.
0 (clear) -
PD1/TCMP1 -- Port D pin 1/TCMP1 select 1 (set) - This pin is configured as Timer output compare 1 output. Setting bit 1 in the COND register makes it an open drain output This pin is configured as I/O pin PD1.
4
0 (clear) -
PD0/TCAP1 -- Port D pin 0/TCAP1 select 1 (set) - This pin is configured as timer input capture 1 input. Clearing bit 0 in the COND register enables the pull-up resistor. This pin is configured as I/O pin PD0.
0 (clear) -
TPG
MC68HC05L28
INPUT/OUTPUT PORTS
MOTOROLA 4-5
4
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 4-6
INPUT/OUTPUT PORTS
MC68HC05L28
5
CORE TIMER
The MC68HC05L28 has a 15-stage ripple counter called the core timer (CTIMER). Features of this timer are: timer overflow, power-on reset (POR), real time interrupt (RTI) with four selectable interrupt rates, and a computer operating properly (COP) watchdog timer.
5
Internal bus 8 Internal processor clock $09 CTCR (Core timer counter) 8 fOP / 210 7-bit counter Overflow detect circuit fOP fOP / 22 (/ 4)
fOP / 217 RTI select circuit $08 CTCSR (Core timer control & status)
fOP / 214
POR TCBP COP Clear
8
CTOF RTIF CTOFE RTIE
0
0
RT1
RT0
COP watchdog timer (/ 8)
Interrupt circuit To reset logic
To interrupt logic
Figure 5-1 Core timer block diagram
TPG
MC68HC05L28
CORE TIMER
MOTOROLA 5-1
As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fOP/1024. The POR signal (tPORL) is also derived from this register, at fOP/4064. The counter register circuit is followed by two more stages, with the resulting clock (fOP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages with a 1-of-4 selector. The output of the RTI circuit is further divided by eight to drive the COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the CTIMER control and status register (CTCSR) at location $08.
5
CTOF (core timer overflow flag) is a clearable, read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set. CTOF is cleared by writing a `0' to it. Writing a `1' has no effect. Reset clears this bit. When CTOFE (core timer overflow flag enable) is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears CTOFE. The core timer counter register (CTCR) is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP/4 and can be used for various functions including a software input capture. Extended time periods can be attained using the CTOF function to increment a temporary RAM storage location simulating a 16-bit (or more) counter. The power-on cycle clears the entire counter chain and begins clocking the counter. After tPORL cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. When RESET is asserted at any time during operation (other than POR), the counter chain is cleared. See Section 5.3 for register details.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock frequency that drives the RTI circuit is fOP/213 (or fOP/8192), with three additional divider stages, giving a maximum interrupt period of 4 seconds at a crystal frequency (fOP) of 32kHz. The flag (RTIF) is a clearable, read-only status bit which is set when the output of the chosen (1-of-4 selection) stage becomes active. A CPU interrupt request is generated if RTIE is set. RTIF is cleared by writing a `0' to it. Writing a `1' has no effect. Reset clears this bit. See Section 5.3 for register details.
TPG
MOTOROLA 5-2
CORE TIMER
MC68HC05L28
5.2
Computer operating properly (COP) watchdog timer
The COP watchdog timer is implemented by dividing the output of the RTI circuit by eight, as shown in Figure 5-1. The minimum COP timeout period is seven times the RTI period. This is because the COP will be cleared asynchronously with respect to the value in the core timer counter register/RTI divider, hence the actual COP timeout period will vary between 7x and 8x the RTI period. See Table 5-1. The COP function is enabled by programming the COPON bit in the option register (OPT). See Section 1.2.1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Writing a `0' to bit 0 of address $0FF0 prevents a COP timeout. When the COP is cleared, only the final divide-by-eight stage is cleared (see Figure 5-1). See Section 5.3 for register details.
5
Table 5-1 Minimum COP reset times
Minimum COP reset at bus frequency: 16.384 kHz 4.194 MHz f OP 7s 53.2 ms 7 x (RTI rate) 17s 105.7 ms 7 x (RTI rate) 28s 765.8 ms 7 x (RTI rate) 56 s 422.8 ms 7 x (RTI rate)
RT1, RT0 00 01 10 11
5.3 5.3.1
Core timer registers Core timer control and status register (CTCSR)
Address bit 7 CTOF bit 6 bit 5 bit 4 bit 3 0 bit 2 0 bit 1 RT1 bit 0 RT0 State on reset
Core timer control/status (CTCSR)
$0008
RTIF CTOFE RTIE
0000 0011
CTOF -- Core timer overflow 1 (set) - The core timer has overflowed. The core timer has not overflowed.
0 (clear) -
This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request will be generated if CTOFE is set. When set, the bit may be cleared by writing a `0' to it.
TPG
MC68HC05L28
CORE TIMER
MOTOROLA 5-3
RTIF -- Real time interrupt flag 1 (set) - A real time interrupt has occurred. No real time interrupt has been generated.
0 (clear) -
This bit is set when the output of the chosen stage becomes active; an interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a `0' to it. CTOFE -- Core timer overflow enable 1 (set) - Core timer overflow interrupt is enabled. Core timer overflow interrupt is disabled.
0 (clear) -
5
Setting this bit enables the core timer overflow interrupt. A CPU interrupt request is generated when the CTOF bit is set. Clearing this bit disables the core timer overflow interrupt capability. RTIE -- Real time interrupt enable 1 (set) - Real time interrupt is enabled. Real time interrupt is disabled.
0 (clear) -
Setting this bit enables the real time interrupt. A CPU interrupt request is generated when the RTIF bit is set. Clearing this bit disables the real time interrupt capability. RT1, RT0 -- Real time interrupt rate select These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0 and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter them if necessary. The COP reset times are also determined by these two bits. Care should be taken when altering RT0 and RT1 if a timeout is imminent or the timeout period is uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing the RTI taps. SeeTable 5-2 for some example RTI periods.
Table 5-2 Example RTI periods
Bus frequency fOP = 2 MHz Minimum RTI period COP period 8.2ms 57.3ms 16.4ms 114.7ms 32.8ms 229.4ms 65.5ms 458.8ms
RT1 0 0 1 1
RT0 0 1 0 1
Division ratio 2 14 2 15 2 16 2 17
TPG
MOTOROLA 5-4
CORE TIMER
MC68HC05L28
5.3.2
Core timer counter register (CTCR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
Core timer counter (CTCR)
$0009
The core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. Reset clears this register.
5.4
Core timer during WAIT
5
The CPU clock halts during the WAIT mode, but the core timer remains active. If the interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt or an external reset, the internal oscillator will restart, followed by an internal processor stabilization delay (tPORL). The timer is then cleared and operation resumes.
TPG
MC68HC05L28
CORE TIMER
MOTOROLA 5-5
5
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 5-6
CORE TIMER
MC68HC05L28
6
16-BIT PROGRAMMABLE TIMER
The MC68HC05L28 has a 16-bit programmable timer. This timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus input capture/output compare circuitry. Selected input edges cause the current counter value to be latched into a 16-bit input capture register so that software can later read this value to determine when the edge occurred. When the free running counter value matches the value in the output compare registers, the programmed pin action takes place. See Figure 6-1 for a block diagram of the timer. As the timer has a 16-bit architecture, each segment is represented by two 8-bit registers. These registers contain the high and low byte of that functional segment. Accessing the low byte of a specific timer function allows full control of that function, while accessing the high byte inhibits that specific timer function until the low byte is also accessed.
6
Note:
The I-bit in the CCR should be set, while manipulating both the high and low byte register of a specific timer function, to ensure that an interrupt does not occur.
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-1
Internal bus 8 Internal processor clock High byte Output compare register 1 Low byte $22 $23 High byte Output compare register 2 Low byte $26 $27 High byte 8-bit buffer Low byte High byte Low byte High byte Low byte
/4
16-bit $28 free-running $29 counter Counter alternate register $2A $2B
Input capture $20 register 1 $21
Input capture $24 register 2 $25
6
Output compare circuit 1 Output compare circuit 2
Internal timer bus
Overflow detect circuit
Edge detect circuit 1
Edge detect circuit 2
TCAP2 pin
TCAP1 pin
D CLK C
Q
TCMP2 pin
D CLK
IC1F IC2F OC1F TOF OCF2
Q
TCMP1 pin
TSR ($2E)
C
RESET IC1IE IC2IE OC1IE TOIE IEDG1 IEDG2 OLVL1
TCR1 ($2C)
Interrupt circuit Interrupt routine
OC2IE
OLVL2
TCR2 ($2D)
Figure 6-1 16-bit programmable timer block diagram
TPG
MOTOROLA 6-2
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
6.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter, or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2s if the internal bus clock is 2MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value.
6.1.1
Counter high register Counter low register Alternate counter high register Alternate counter low register
Address bit 7 (bit 15) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (bit 8) State on reset $FF $FC (bit 8) $FF $FC
6
Timer counter high (TCH) Timer counter low (TCL) Alternate counter high (ACH) Alternate counter low (ACL)
$0028 $0029
$002A (bit 15) $002B
The double-byte, free-running counter can be read from either of two locations: the counter register at $28-$29 or the alternate counter register at $2A-$2B. A read from only the less significant byte (LSB) of the free-running counter, $29 or $2B, receives the count value at the time of the read. If a read of the free-running counter or alternate counter register first addresses the more significant byte (MSB), $28 or $2A, the LSB is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the free-running counter or alternate counter register LSB and thus completes a read sequence of the total counter value. In reading either the free-running counter or alternate counter register, if the MSB is read, the LSB must also be read to complete the sequence. The alternate counter register differs from the counter register only in that a read of the MSB does not clear TOF. Therefore the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of TOF. If the timer overflow flag (TOF) is set when the counter register LSB is read, then a read of the TSR will clear the flag. The free-running counter is set to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the free-running counter repeats every 262144 internal bus clock cycles. TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-3
Bits 8-15 -- MSB of counter/alternate counter register A read of only the more significant byte (MSB) transfers the LSB to a buffer, which remains fixed after the first MSB read, until the LSB is also read. Bits 0-7 -- LSB of counter/alternate counter register A read of only the less significant byte (LSB) receives the count value at the time of reading.
6.2
Timer functions
The 16-bit programmable timer is monitored and controlled by a group of fifteen registers, full details of which are contained in the following paragraphs. An explanation of the timer functions is also given.
6
6.2.1 Timer control registers
The timer control registers at locations $2C and $2D are read/write registers. Five bits control interrupts associated with the timer status register flags IC1F, IC2F, OC1F, OC2F and TOF. Two bits control which edge is significant to the input capture 1 and 2 edge detectors.
6.2.1.1 Timer control register 1 (TCR1)
Address Timer control 1 (TCR1) $002C bit 7 IC1IE bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
IC2IE OC1IE TOIE
CO1E IEDG1 IEDG2 OLVL1 0000 0uu0
IC1IE -- Input capture 1 interrupt enable 1 (set) - Input capture 1 interrupt enabled. Input capture 1 interrupt disabled.
0 (clear) -
IC2IE -- Input capture 2 interrupt enable 1 (set) - Input capture 2 interrupt enabled. Input capture 2 interrupt disabled.
0 (clear) -
OC1IE -- Output compare 1 interrupt enable 1 (set) - Output compare 1 interrupt enabled. Output compare 1 interrupt disabled.
0 (clear) -
TPG
MOTOROLA 6-4
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
TOIE -- Timer overflow interrupt enable 1 (set) - Timer overflow interrupt enabled. Timer overflow interrupt disabled.
0 (clear) -
CO1E -- Timer compare 1 output enable 1 (set) - Output of timer compare 1 is enabled. Output of timer compare 1 is disabled.
0 (clear) - Reset clears this bit.
IEDG1 -- Input edge 1 This bit determines which level transition on TCAP1 pin will trigger the transfer of the free-running counter to input capture register. 1 (set) - TCAP1 is rising edge sensitive. TCAP1 is falling edge sensitive.
6
0 (clear) -
When IEDG1 is set, a rising edge on the TCAP1 pin will trigger a transfer of the free-running counter value to the input capture register. When clear, a falling edge triggers the transfer. Reset does not affect the IEDG1 bit. IEDG2 -- Input edge 2 This bit determines which level transition on TCAP2 pin will trigger the transfer of the free-running counter to input capture register 2. 1 (set) - TCAP2 is rising edge sensitive. TCAP2 is falling edge sensitive.
0 (clear) -
When IEDG2 is set, a rising edge on the TCAP2 pin will trigger a transfer of the free-running counter value to the input capture register. When clear, a falling edge triggers the transfer. Reset does not affect the IEDG2 bit. OLVL1 -- Output level 1 This bit determines the level that is clocked into the output level register by the next successful output compare 1 and which will appear on the TCMP1 pin. 1 (set) - A high output level will appear on the TCMP1 pin. A low output level will appear on the TCMP1 pin.
0 (clear) -
When OLVL1 is set, a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level that will appear on the TCMP1 pin.
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-5
6.2.1.2 Timer control register 2 (TCR2)
Address Timer control 2 (TCR2) $002D bit 7 0 bit 6 0 bit 5 OC2IE bit 4 0 bit 3 CO2E bit 2 0 bit 1 0 bit 0 State on reset
OLVL2 0000 0000
OC2IE -- Output compare 2 interrupt enable 1 (set) - Output compare 2 interrupt enabled. Output compare 2 interrupt disabled.
0 (clear) -
CO2E -- Timer compare 2 output enable 1 (set) - Output of timer compare 2 is enabled. Output of timer compare 2 is disabled.
6
0 (clear) - Reset clears this bit.
OLVL2 -- Output level 2 This bit determines the level that is clocked into the output level register by the next successful output compare 2 and which will appear on the TCMP2 pin. 1 (set) - A high output level will appear on the TCMP2 pin. A low output level will appear on the TCMP2 pin.
0 (clear) -
When OLVL2 is set, a high output level will be clocked into the output level register by the next successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level that will appear on the TCMP2 pin. Bits 1, 2 4, 6 and 7 -- unused; always read 0.
TPG
MOTOROLA 6-6
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
6.2.2
Timer status register (TSR)
The timer status register ($2E) contains the status bits for the interrupt conditions -- ICF, OCF, TOF. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit.
Address Timer status (TSR) $002E bit 7 IC1F bit 6 IC2F bit 5 OC1F bit 4 bit 3 bit 2 bit 1 0 bit 0 State on reset
TOF TCAP1 TCAP2 OC2F
uuuu 11u0
IC1F -- Input capture 1 flag 1 (set) - Valid input capture has occurred. No input capture has occurred.
0 (clear) -
This bit is set when the selected polarity of edge is detected by the input capture 1 edge detector; an input capture interrupt will be generated, if IC1IE is set. IC1F is cleared by reading the TSR and then the input capture low 1 register at $21. IC2F -- Input capture 2 flag 1 (set) - Valid input capture has occurred. No input capture has occurred.
6
0 (clear) -
This bit is set when the selected polarity of edge is detected by the input capture 2 edge detector; an input capture interrupt will be generated, if IC2IE is set. IC2F is cleared by reading the TSR and then the input capture low 2 register at $25. OC1F -- Output compare 1 flag 1 (set) - A valid output compare has occurred. No output compare has occurred.
0 (clear) -
This bit is set when the output compare register contents match those of the free-running counter; an output compare interrupt will be generated, if OC1IE is set. OC1F is cleared by reading the TSR and then the output compare low 1 register at $23. TOF -- Timer overflow flag 1 (set) - Timer overflow has occurred. No timer overflow has occurred.
0 (clear) -
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt will occur, if TOIE is set. TOF is cleared by reading the TSR and the counter low register at $29.
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-7
When using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: - - the timer status register is read or written when TOF is set and the LSB of the free-running counter is read, but not for the purpose of servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential problem. TCAP1 -- Timer capture 1 This bit reflects the current status of the timer capture 1 input.
Note:
6
Note:
On the MC68HC05L28, TCAP1 is connected directly to PD0 which defaults to an input with pull-up on reset. TCAP1 will be `1' unless PD0 is externally driven low.
TCAP2 -- Timer capture 2 This bit reflects the current state of the timer capture 2 Input. On the MC68HC05L28, TCAP2 is connected directly to PD2 which defaults to an input with pull-up on reset. TCAP2 will be `1' unless PD2 is externally driven low.
OC2F -- Output compare 2 flag 1 (set) - A valid output compare has occurred. No output compare has occurred.
0 (clear) -
This bit is set when the output compare register contents match those of the free-running counter; an output compare interrupt will be generated, if OC2IE is set. OC2F is cleared by reading the TSR and then the output compare low 2 register at $27. Bit 0 -- always reads zero.
TPG
MOTOROLA 6-8
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
6.2.3
Input capture registers
`Input capture' is a technique whereby an external signal (connected to the TCAP1 or TCAP2 pin) is used to trigger a read of the free-running counter. In this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. There are two identical input capture registers.
6.2.3.1 Input capture register 1
Address Input capture high 1 (ICH1) Input capture low 1 (ICL1) $0020 $0021 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Unaffected Unaffected
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a valid transition. The level transition that triggers the counter transfer is defined by the input edge bit (IEDG1). The most significant 8 bits are stored in the input capture high 1 register at $20 and the least significant in the input capture low 1 register at $21. An interrupt can accompany a capture if the corresponding interrupt enable bit (IC1IE in timer control register 1 at $2C) is set. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronisation. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture 1 flag (IC1F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register MSB ($20), the counter transfer is inhibited until the LSB ($21) is also read. This causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($21) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture register, except when exiting STOP mode.
6
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-9
6.2.3.2 Input capture register 2
Address Input capture high 2 (ICH2) Input capture low 2 (ICL2) $0024 $0025 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Unaffected Unaffected
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a valid transition. The level transition that triggers the counter transfer is defined by the input edge bit (IEDG2). The most significant 8 bits are stored in the input capture high 2 register at $24 and the least significant in the input capture low 2 register at $25. An interrupt can accompany a capture if the corresponding interrupt enable bit (IC2IE in timer control register 1 at $2C) is set.
6
The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronisation. Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture 2 flag (IC2F) is set or clear. The input capture register always contains the free-running counter value that corresponds to the most recent input capture. After a read of the input capture register MSB ($24), the counter transfer is inhibited until the LSB ($25) is also read. This causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($25) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. Reset does not affect the contents of the input capture register, except when exiting STOP mode.
TPG
MOTOROLA 6-10
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
6.2.4
Output compare registers
`Output compare' is a technique that may be used, for example, to generate an output waveform, or to signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. There are two output compare registers - OC1 and OC2. All the bits are readable and writable and are not altered by the timer hardware or reset. If the compare function is not needed, the two bytes of the output compare register can be used as storage locations.
6.2.4.1 Output compare register 1
Address Output compare high 1 (OCH1) Output compare low 1 (OCL1) $0022 $0023 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Unaffected Unaffected
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $22 (MSB) and $23 (LSB). The contents of the output compare 1 register are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare 1 flag (OC1F) in the timer status register is set and the output level 1 (OLVL1) bit is clocked to the TCMP1 pin. The output compare 1 register values and the output level 1 bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OC1IE) is set. After a processor write cycle to the output compare register 1 containing the MSB ($22), the output compare function is inhibited until the LSB ($23) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB will not inhibit the compare function. The processor can write to either byte of the output compare register 1 without affecting the other byte. The output level 1 bit (OLVL1) is clocked to the output level 1 register whether the output compare 1 flag (OC1F) is set or clear. The minimum time required to update the output compare 1 register is a function of the program rather than the internal hardware. Because the output compare 1 flag and the output compare 1 register are not defined at power on, and not affected by reset, care must be taken when initialising output compare functions with software. The following procedure is recommended: 1) write to output compare high 1 to inhibit further compares; 2) read the timer status register to clear OC1F (if set); 3) write to output compare low 1 to enable the output compare 1 function.
6
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-11
6.2.4.2 Output compare register 2
Address Output compare high 2 (OCH2) Output compare low 2 (OCL2) $0026 $0027 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Unaffected Unaffected
6
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $26 (MSB) and $27 (LSB). The contents of the output compare 2 register are compared with the contents of the free-running counter once every four internal processor clock cycles. If a match is found, the output compare 2 flag (OC2F) in the timer status register is set and the output level 2 (OLVL2) bit is clocked to the TCMP2 pin. The output compare 2 register values and the output level 2 bit should be changed after each successful comparison to establish a new elapsed timeout. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OC2IE) is set. After a processor write cycle to the output compare register 1 containing the MSB ($26), the output compare function is inhibited until the LSB ($27) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB will not inhibit the compare function. The processor can write to either byte of the output compare 2 register without affecting the other byte. The output level 2 bit (OLVL2) is clocked to the output level 2 register whether the output compare 2 flag (OC2F) is set or clear. The minimum time required to update the output compare 2 register is a function of the program rather than the internal hardware. Because the output compare 2 flag and the output compare 2 register are not defined at power on, and not affected by reset, care must be taken when initialising output compare functions with software. The following procedure is recommended: - - - write to output compare high 2 to inhibit further compares; read the timer status register to clear OC2F (if set); write to output compare low 2 to enable the output compare 2 function. As the TCMP1 and TCMP2 pins are shared with port D, output compares 1 and 2 cannot be used for compare when the pins are selected to be input. However, the data register can still be used as a temporary store.
Note:
TPG
MOTOROLA 6-12
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
6.3
Timer during WAIT mode
In WAIT mode all CPU action is suspended, whereas the timer continues to run.
6.4
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, so the timer stops counting. If STOP is exited by an interrupt the counter retains the last count value. If the device is reset, the counter is forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any timer flags nor wake up the MCU. When the MCU does wake up, however, there is an active input capture flag and data from the first valid edge that occurred during the STOP period. If the device is reset to exit STOP mode, no input capture flag or data remains, even if a valid input capture edge occurred.
6
6.5
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following diagrams. It should be noted that the signals labelled `internal' (processor clock, timer clocks and reset) are not available to the user.
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-13
Internal processor clock Internal reset
Internal timer clocks
T00 T01 T10 T11
$FFFC $FFFD $FFFE $FFFF
16-bit counter External reset or end of POR
6
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
Figure 6-2 Timer state timing diagram for reset
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$F123 $F124 $F125 $F126
16-bit counter Input edge Internal capture latch Input capture register Input capture flag
}
$????
}
}
} $F124
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture flag will be set during the next T11 state.
Figure 6-3 Timer state timing diagram for input capture
TPG
MOTOROLA 6-14
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$F456
(Note 1)
16-bit counter Output compare register Compare register latch Output compare flag and TCMP
$F457
$F458
$F459
CPU writes $F457
(Note 1)
$F457
(Note 2)
6
Note:
(1) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare. (2) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example).
Figure 6-4 Timer state timing diagram for output compare
Internal processor clock
Internal timer clocks
T00 T01 T10 T11
$FFFF $0000 $0001 $0002
16-bit counter Timer overflow flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleare by a read of the timer status register during the internal processor clock high time, followed by a rea of the counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
TPG
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
MOTOROLA 6-15
6
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 6-16
16-BIT PROGRAMMABLE TIMER
MC68HC05L28
7
LIQUID CRYSTAL DISPLAY DRIVER MODULE
This chapter describes the generic M68HC05 family LCD driver module. Any differences in the module specific to the MC68HC05L28 are indicated along with the generic description. The M68HC05 family LCD driver module can be configured with up to 24 frontplane drivers and a maximum of 4 backplane drivers. This allows a maximum of 96 LCD segments. The LCD driver module on the MC68HC05L28 supports 18 frontplanes and 4 backplanes, allowing a maximum of 72 LCD segments. Each segment is controlled by a corresponding bit in the LCD RAM. The mode of operation is determined by the values set in the LCD control register at $1E. At reset or on power-up, the drivers are configured in the default duplex mode, 1/2 bias with 2 backplanes and 18 frontplanes. Also at power-up or reset the ON/OFF control for the display, the DISON bit in the LCD control (LCD) register, is cleared disabling the LCD drivers. Figure 7-1 shows a block diagram of the LCD system.
7
Internal data bus Internal address bus 13
8
Internal signals Control logic
LCD RAM
Backplane driver
BP3 BP2 BP1 BP0
Segment driver
Voltage generator
V LCD
FP17
FP0
Figure 7-1 LCD system block diagram
TPG
MC68HC05L28
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MOTOROLA 7-1
7.1
LCD RAM
Data to be displayed on the LCD must be written into the LCD RAM. The LCD RAM is comprised of 12 bytes of RAM (in the MC68HC05L28's memory map) at $0040 - $004B. The 96 bits in the LCD RAM correspond to the 96 segments that can be driven by the frontplane/backplane drivers. Table 7-1 shows how the LCD RAM is organized. Writing a `1' to a given location will result in the corresponding display segment being activated when the DISON bit is set. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. When DISON = 0, the LCD RAM can be used as main on-chip RAM.
Table 7-1 LCD RAM organization
LCD RAM Address
$40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B
Data bit 7
FP1-BP3 FP3-BP3 FP5-BP3 FP7-BP3 FP9-BP3 FP11-BP3 FP13-BP3 FP15-BP3 FP17-BP3 FP19-BP3 FP21-BP3 FP23-BP3
bit 6
FP1-BP2 FP3-BP2 FP5-BP2 FP7-BP2 FP9-BP2 FP11-BP2 FP13-BP2 FP15-BP2 FP17-BP2 FP19-BP2 FP21-BP2 FP23-BP2
bit 5
FP1-BP1 FP3-BP1 FP5-BP1 FP7-BP1 FP9-BP1 FP11-BP1 FP13-BP1 FP15-BP1 FP17-BP1 FP19-BP1 FP21-BP1 FP23-BP1
bit 4
FP1-BP0 FP3-BP0 FP5-BP0 FP7-BP0 FP9-BP0 FP11-BP0 FP13-BP0 FP15-BP0 FP17-BP0 FP19-BP0 FP21-BP0 FP23-BP0
bit 3
FP0-BP3 FP2-BP3 FP4-BP3 FP6-BP3 FP8-BP3 FP10-BP3 FP12-BP3 FP14-BP3 FP16-BP3 FP18-BP3 FP20-BP3 FP22-BP3
bit 2
FP0-BP2 FP2-BP2 FP4-BP2 FP6-BP2 FP8-BP2 FP10-BP2 FP12-BP2 FP14-BP2 FP16-BP2 FP18-BP2 FP20-BP2 FP122-BP2
bit 1
FP0-BP1 FP2-BP1 FP4-BP1 FP6-BP1 FP8-BP1 FP10-BP1 FP12-BP1 FP14-BP1 FP16-BP1 FP18-BP1 FP20-BP1 FP22-BP1
bit 0
FP0-BP0 FP2-BP0 FP4-BP0 FP6-BP0 FP8-BP0 FP10-BP0 FP12-BP0 FP14-BP0 FP16-BP0 FP18-BP0 FP20-BP0 FP22-BP0
7
These LCD pins are not available on the MC68HC05L28/ MC68HC705L28. The corresponding RAM bytes ($49 to $4B) can continue to be used as main on-chip RAM.
7.2
LCD operation
The LCD driver module can operate in four modes providing different multiplex ratios and number of backplanes as follows: * * * * 1/2 bias, 2 backplanes 1/3 bias, 2 backplanes 1/3 bias, 3 backplanes 1/4 bias, 4 backplanes
TPG
MOTOROLA 7-2
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MC68HC05L28
The operating mode is selected at power on using the multiplex ratio bits (MUX3 and MUX4) in the LCD control register as shown in Table 7-2. It is recommended that the DISON bit in the LCD register is not set (display is disabled) until the multiplex rate is selected. The voltage levels required for the different multiplex rates are generated internally by a resistive divider chain between VLCD, VDD and VSS. The 2-way multiplex with 1/3 bias and the three and four-way multiplex options require four voltage levels, whereas the two-way multiplex with 1/2 bias needs only three levels. Resistors R1, R2 and R3 are valued at 25k 40%. Figure 7-2 shows the resistive divider chain network that is used to produce the various LCD waveforms outlined in Section 7.3.
Note: Note:
VLCD may not exceed the positive power supply voltage VDD. The VLCD option is not available on the MC68HC05L28 or MC68HC705L28, but is included here for completeness of the generic module description. Bit 6 of the LCD control register must be cleared.
VLCD
Bit 0, $1E
VDD
7
Bit 6, $1E
R3 V2 2 BP, 1/2 Bias R2 V1 R1
VSS Figure 7-2 Voltage level selection
7.3
Timing signals and LCD voltage waveforms
The LCD timing signals are all derived from the main system clock; with a bus frequency of 2 MHz (fosc = 4 MHz) the frame rate will be 61 Hz for 2 and 4-way multiplexing and 91 Hz for 3-way multiplexing (see Table 7-2). An extra divide-by-two stage can be included in the LCD clock generator by setting FDISP in the LCD register. This will result in the frame rate being halved. For
TPG
MC68HC05L28
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MOTOROLA 7-3
example, when 3-way multiplexing is used, a frame rate of 45.5 Hz instead of 91 Hz can be obtained. See Section 7.4. Figure 7-3 to Figure 7-6 show the backplane waveforms and some examples of frontplane waveforms for each of the operating modes. The backplane waveforms are continuous and repetitive (every 2 frames); they are fixed within each operating mode and are not affected by the data in the LCD RAM. The frontplane waveforms are dependent on the LCD segments to be driven as defined in the LCD RAM. Each "on" segment must have a differential driving voltage (BP-FP) applied to it once in each frame; the LCD driver module hardware uses the data in the LCD RAM to construct the frontplane waveform to meet this criterion.
V DD /VLCD
BP0
V2 V0
V DD /VLCD
7
BP1
V2 V0
ON OFF
V DD /VLCD
FPx, example 1
1 Frame
V2 V0
V DD /VLCD
FPx, example 2
V2 V0
V DD /VLCD
FPx, example 3
V2 V0
V DD /VLCD
FPx, example 4
V2 V0
Note:
In this mode V1=V2
Figure 7-3 LCD waveform with 2 backplanes, 1/2 bias
TPG
MOTOROLA 7-4
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MC68HC05L28
V DD /VLCD
BP0
V2 V1 V0
V DD /VLCD
BP1
V2 V1 V0
ON OFF 1 Frame
FPx, example 1
V2 V1
V DD /VLCD
FPx, example 2
V2 V1 V0
7
V DD /VLCD
FPx, example 3
V2 V1 V0
V DD /VLCD V2
FPx, example 4
V1 V0
Figure 7-4 LCD waveform with 2 backplanes, 1/3 bias
TPG
MC68HC05L28
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MOTOROLA 7-5
V DD /VLCD V2
BP0
V1 V0
V DD /VLCD
BP1
V2 V1 V0
V DD /VLCD V2
ON OFF 1 Frame
BP2
V1 V0
7
FPx, example 1
V DD /VLCD V2 V1 V0
V DD /VLCD V2
FPx, example 2
V1 V0
V DD /VLCD V2
FPx, example 3
V1 V0
Figure 7-5 LCD waveform with 3 backplanes
TPG
MOTOROLA 7-6
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MC68HC05L28
V DD /VLCD
BP0
V2 V1 V0 V DD /VLCD
BP1
V2 V1 V0 V DD /VLCD
ON OFF 1 Frame
BP2
V2 V1 V0 V DD /VLCD V2
BP3
V1 V0 V DD /VLCD
7
FPx, example 1
V2 V1 V0
V DD /VLCD V2
FPx, example 2
V1 V0
V DD /VLCD V2
FPx, example 3
V1 V0
Figure 7-6 LCD waveform with 4 backplanes
TPG
MC68HC05L28
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MOTOROLA 7-7
7.4
LCD control register
Address LCD control register (LCD) $001E bit 7 bit 6
VLCDON
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on reset
FDISP MUX4 MUX3 DISON ?000 0000
VLCDON -- LCD voltage select The VLCD option is not available on the MC68HC05L28 or MC68HC705L28, therefore, this bit must be cleared. FDISP -- Display frequency 1 (set) - An extra divide by two stage is included in the LCD clock generator to give a reduced frame rate. For example, in the 3-way multiplexing mode, a frame rate of 45.5 Hz instead of 91 Hz can be achieved. Default frame rate is used.
0 (clear) -
7
MUX4, MUX3 -- Multiplex ratio These two bits select the multiplex ratio to be 2, 3 or 4 backplanes. Table 7-2 Multiplex ratio/backplane selection
MUX4 0 0 1 1 MUX3 0 1 0 1 Backplanes 2 3 4 2 Bias 1/2 1/3 1/3 1/3 Frequency 61 Hz 91 Hz 61 Hz 61 Hz
DISON -- Display ON/OFF 1 (set) - Display is ON. Display is OFF
0 (clear) - Reserved bits
Bits 4, 5 and 7 are reserved for future use and must be set to 0 when writing to this register.
7.5
LCD during WAIT mode
The LCD does not function during WAIT mode.
TPG
MOTOROLA 7-8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
MC68HC05L28
I2C-BUS
I2C-bus is a two-wire, bidirectional serial bus that provides a simple, efficient way to exchange data between devices. Being a two-wire device, the I2C-bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. The bus is suitable for applications involving frequent communications between a number of devices over short distances. The number of devices connected to the I2C-bus is limited only by a maximum bus capacitance of 400pF; it has a maximum data rate of 100 kbits per second. The I2C-bus system is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters attempt to control the bus simultaneously. This feature provides the capability for complex applications with multiprocessor control. It may also be used for rapid testing and alignment of end products via external connections to an assembly line computer. The I2C-bus function is enabled by the MEN bit in the I2C-bus control register (MCR).
8
8
8.1
* * * * * * * * * *
I2C-bus features
Multi-master operation Software-programmable for one of 32 different serial clock frequencies Software-selectable acknowledge bit Interrupt-driven, byte-by-byte data transfer Arbitration-lost-driven interrupt with automatic switching from master to slave mode Calling address identification interrupt Generates/detects the START or STOP signal Repeated START signal generation Generates/recognizes the acknowledge bit Bus busy detection
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-1
8.2
I2C-bus system configuration
The I2C-bus system uses a serial data line and a serial clock line for data transfer. All the devices connected to it must have open drain or open collector outputs. A logic `AND' function is used on both lines with two pull-up resistors.
8.3
I2C-bus protocol
A standard communication is normally composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. These signals are described in the following sections and illustrated in Figure 8-1.
8.3.1
START signal
When the bus is free (no master device engaging the bus; SCL and SDA lines at a logic high), a master may initiate communication by sending a START signal, which is defined as being a high to low transition of SDA with SCL high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves.
8
8.3.2
Transmission of the slave address
The first byte of data transferred after the START signal is the slave address transmitted by the master. This address is seven bits long, followed by a R/W bit which tells the slave the desired direction of transfer of all the following bytes (until a STOP or repeated start). Only the slave with the calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 8-1).
TPG
MOTOROLA 8-2
I2C-BUS
MC68HC05L28
MC68HC05L28
acknowledge bit MSB LSB MSB LSB acknowledge bit MSB LSB MSB LSB repeated START signal
no acknowledge
SCL
SDA
START signal
STOP signal
Figure 8-1 I2C bus transmission signal diagrams
I2C-BUS
no acknowledge
SCL
SDA
START signal
STOP signal
TPG
MOTOROLA 8-3
8
8.3.3
Data transfer
Once successful slave addressing has been achieved, the data transfer can proceed byte by byte, in the direction specified by the R/W bit. Data can be changed only when SCL is low and must be held stable while SCL is high. The MSB is transmitted first. Each data byte is eight bits long, and there is one clock pulse on SCL for each data bit. Every byte of data must be followed by an acknowledge bit, which the receiving device signals by pulling SDA low at the ninth clock. Therefore, one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, then the SDA line is left high by the slave. The master can then generate a STOP signal to abort the data transfer or a START signal to commence a new calling (called a repeated start). If the master receiver does not acknowledge the slave transmitter after one byte of transmission, it means `end of data' to the slave, which then releases the SDA line so that the master can generate the STOP or START signal.
8.3.4
STOP signal
8
The master can terminate the communication by generating a STOP signal to free the bus. A STOP signal is defined as a low to high transition of SDA while SCL is high (see Figure 8-1).
8.3.5
Repeated START signal
A repeated START signal generates a START signal without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave, or with the same slave in a different mode (transmit/receive mode), without releasing the bus.
8.3.6
Arbitration procedure
The I2C-bus is a true multi-master system that allows more than one master to be connected to it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high period is equal to the shortest clock high period among the masters. A data arbitration procedure determines the relative priority of the contending masters; a master loses arbitration if it transmits logic 1 while another transmits logic 0. The losing masters then immediately switch to slave receive mode and stop driving SDA outputs. The transition from master to slave mode does not generate a STOP condition in this case. At this point, the MAL bit in the I2C-bus status register (MSR) is set by hardware to indicate loss of arbitration.
TPG
MOTOROLA 8-4
I2C-BUS
MC68HC05L28
8.3.7
Clock synchronization
Since wired-AND logic is performed on the SCL line, a high to low transition on SCL affects all the devices connected on the bus. The devices start counting their low period and once a device's clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 8-2). When all devices concerned have counted off their low period, the SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line, and all of them start counting their high periods. The first device to complete its high period pulls the SCL line low again.
Start counting high period SCL1 Wait
SCL2
Internal counter register SCL
8
Figure 8-2 Clock synchronization
8.3.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. The slave device may hold SCL low after the completion of one byte of data transfer (nine bits). In such cases, it halts the bus clock and forces the master clock into a wait state until the slave releases the SCL line.
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-5
8.4 8.4.1
Registers I2C-bus address register (MADR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 000u
I2C-bus address register (MADR)
$0010
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
ADR7 - ADR1 -- Slave address bits These bits define the slave address of the I2C-bus, and are used in slave mode in conjunction with the MAAS bit in the MSR register (see Section 8.4.4). These bits can be read and written at any time. Bit 0 -- reserved by Motorola.
8.4.2
I2C-bus frequency divider register (FDR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
I2C-bus frequency divider register (FDR) $0011
MBC4 MBC3 MBC2 MBC1 MBC0 uuu0 0000
8
MBC4 - MBC0 -- Clock rate select bits These bits can be read and written at any time. These bits are used to prescale the clock for bit rate selection. Due to the potential slow rise and fall times of the SCL and SDA signals the bus signals are sampled at the prescaler frequency. This sampling incurs an overhead of six clocks per SCL pulse. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 8-1, plus the sampling overhead of six clocks per cycle. For a 4 MHz external crystal operation, the serial bit clock frequency of the I2C-bus ranges from 460 Hz to 90909 kHz.
TPG
MOTOROLA 8-6
I2C-BUS
MC68HC05L28
Table 8-1 I2C-bus prescaler
MCB4-0 00000 00001 00010 00011 00100 00101 00110 00111 Divider 22 24 28 34 44 48 56 68 MCB4-0 Divider 01000 88 01001 96 01010 112 01011 136 01100 176 01101 192 01110 224 01111 272 MCB4-0 Divider 10000 352 10001 384 10010 448 10011 544 10100 704 10101 768 10110 896 10111 1088 MCB4-0 Divider 11000 1408 11001 1536 11010 1792 11011 2176 11100 2816 11101 3072 11110 3584 11111 4352
8.4.3
I2C-bus control register (MCR)
These bits can be read and written at any time.
Address bit 7 I2C-bus control register (MCR) $0012 MEN bit 6 bit 5 bit 4 MTX bit 3 TXAK bit 2 bit 1 bit 0 State on reset 0000 0uuu
MIEN MSTA
MEN -- I2C-bus enable 1 (set) - interface system is enabled. This bit must be set before any other MCR bits can be set. I2C-bus interface system is disabled and reset. This is the power-on reset case. When low, the interface is held in reset, but registers can be accessed. I2C-bus
8
0 (clear) -
If the module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating when a subsequent start condition is detected. Master mode is not aware that the bus is busy, so if a start cycle is initiated the current bus cycle may become corrupt. This results in either the current bus master or the I2C-bus losing arbitration, after which bus operation returns to normal. MIEN -- I2C-bus interrupt enable 1 (set) - I2C-bus interrupt is requested when MIF is set. I2C-bus interrupt is disabled.
0 (clear) -
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-7
MSTA -- Master/slave mode select 1 (set) - Master mode; send START signal when set. Slave mode; send STOP signal when cleared.
0 (clear) -
This bit is cleared on reset. When MSTA is changed from 0 to a 1, a START signal is generated on the bus and the master mode is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the slave mode is selected. In master mode, clearing MSTA and then immediately setting it generates a repeated START signal without generating a STOP signal (see Figure 8-1). MTX -- Transmit/receive mode select 1 (set) - Transmit mode. Receive mode.
0 (clear) -
TXAK -- Transmit acknowledge bit 1 (set) - No acknowledge signal response. An acknowledge signal will be sent to the bus at the ninth clock bit after receiving one byte of data.
0 (clear) -
This bit only has meaning in master receive mode.
8
Bits 2-0 -- not implemented; always read zero.
8.4.4
I2C-bus status register (MSR)
Address bit 7 bit 6 bit 5 bit 4 MAL bit 3 bit 2 SRW bit 1 MIF bit 0 State on reset
I2C-bus status register (MSR)
$0013
MCF MAAS MBB
RXAK 1000 u001
Bits in this register can be read at any time; Bits 4 and 1 can be cleared at any time. MCF -- Data transferring 1 (set) - Data transmit complete. Data is being transferred.
0 (clear) -
MAAS -- I2C-bus addressed as a slave 1 (set) - I2C-bus is addressed as a slave. I2C-bus is not addressed.
0 (clear) -
This bit is set when the address of the I2C-bus (specified in MADR) matches the calling address. An interrupt is generated providing the MIEN bit in the MCR register is set; the CPU then selects its transmit/receive mode according to the state of the SRW bit. Writing to the MCR register clears this bit.
TPG
MOTOROLA 8-8
I2C-BUS
MC68HC05L28
MBB -- Bus busy 1 (set) - Bus is busy. Bus is idle.
0 (clear) -
This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a STOP signal is detected, MBB is cleared. MAL -- Arbitration lost 1 (set) - Arbitration lost. Default state.
0 (clear) -
MAL is set by hardware when the arbitration procedure is lost during a master transmission mode. This bit must be cleared by software. Bit 3 -- Not implemented; always reads zero. SRW -- Read/write command 1 (set) - R/W command bit is set (read). R/W command bit is clear (write).
0 (clear) -
When MAAS is set, the R/W command bit of the calling address sent from a master is latched into this bit. On checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. MIF -- I2C-bus interrupt flag 1 (set) - An I2C-bus interrupt is pending. No I2C-bus interrupt is pending.
8
0 (clear) -
When this bit is set, an I2C-bus interrupt is generated provided the MIEN bit in the MCR register is set. MIF is set when one of the following events occurs: 1) The transfer of one byte of data is complete; MIF is set at the falling edge of the ninth clock after the byte has been received. 2) A calling address is received which matches the address of the I2C-bus in slave receive mode. 3) Arbitration is lost. MIF must be cleared by software in the interrupt routine. RXAK -- Received acknowledge bit 1 (set) - No acknowledge signal has been detected at the ninth clock after the transmission of a byte of data. An acknowledge bit has been received at the ninth clock after the transmission of a byte of data.
TPG
0 (clear) -
MC68HC05L28
I2C-BUS
MOTOROLA 8-9
8.4.5
I2C-bus data register (MDR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
I2C-bus data register (MDR)
$0014 TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 Undefined
These bits can be read and written at any time. In master transmit mode, a write to this register will cause the data in it to be sent to the bus automatically, MSB first. In master receive mode, a read of this register initiates the transfer of the next incoming byte of data into the register. See Figure 8-3. In slave transmit mode, the SCL line is forced low until data is written into this register, to prevent transmission. Similarly, in slave receive mode, the data bus must be read before a transmission can occur.
8.5 8.5.1
Programming Initialization
8
After a reset, the I2C-bus control register (MCR) is in a default state. Before the I2C-bus can be used, it must be initialized as follows: 1) Configure the frequency divider register for the desired SCL frequency. 2) Configure the I2C-bus address register (MADR) to define the slave address of the I2C-bus. 3) Set the MEN bit in the I2C-bus control register (MCR) to enable the I2C-bus system. 4) Configure the other bits in the MCR register.
8.5.2
START signal and the first byte of data
After the initialization procedure has been completed, serial data can be transmitted by selecting the `master transmitter' mode. If the device is connected to a multi-master bus system, the state of the I2C-bus busy bit (MBB) must be tested to check whether the serial bus is free. If the bus is free (MBB = 0), the START condition and the first byte (the slave address) can be sent. An example of a program that does this is shown below: CHFLAG SEI BRSET 5,MSR,CHFLAG ;DISABLE INTERRUPT ;CHECK THE MBB BIT OF THE STATUS ;REGISTER. IF IT IS SET, WAIT
TPG
MOTOROLA 8-10
I2C-BUS
MC68HC05L28
TXSTART
BSET BSET LDA STA CLI
4,MCR 5,MCR CALLING MDR
;UNTIL IT IS CLEAR ;SET TRANSMIT MODE ;SET MASTER MODE ;i.e. GENERATE START CONDITION ;GET THE CALLING ADDRESS ;TRANSMIT THE CALLING ADDRESS ;ENABLE INTERRUPT
8.5.3
Software response
The transmission or reception of a byte sets the data transferring bit, MCF, which indicates that one byte of communication is finished. Also, the I2C-bus interrupt bit, MIF, is set to generate an I2C-bus interrupt (if MIEN is set). Figure 8-3 shows an example of a typical I2C-bus interrupt routine. In the interrupt routine, the first step is for software to clear the MIF bit. The MCF bit can be cleared by reading from the I2C-bus data I/O register (MDR) in receive mode, or by writing to MDR in transmit mode. Software may service the I2C-bus I/O in the main program by monitoring the MIF bit if the interrupt function is disabled. The following is an example of a software response by a `master transmitter' in the interrupt routine: ISR BCLR BRCLR BRCLR BRSET 1,MSR 5,MCR,SLAVE ;CLEAR THE MIF FLAG ;CHECK THE MSTA FLAG ;BRANCH IF SLAVE MODE 4,MCR,RECIEVE ;CHECK THE MODE FLAG 0,MSR,END ;CHECK ACKNOWLEDGE FROM ;RECEIVER ;IF NO ACKNOWLEDGE, END :TRANSMISSION DATABUF ;GET THE NEXT BYTE OF DATA
8
TRANSMIT
LDA
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-11
8.5.4
Generation of a STOP signal
A data transfer ends with a STOP signal generated by the master device. A master transmitter can simply generate a STOP signal after all the data has been transmitted; for example: MASTX BRSET LDAA BEQ LDAA STAA DEC BRA BCLR RTI 0,MSR,END TXCNT END DATABUF MDR TXCNT EMASTX 5,MCR ;IF NO ACKNOWLEDGEMENT, ;BRANCH TO END ;GET VALUE FROM THE ;TRANSMITTING COUNTER ;IF NO MORE DATA, BRANCH TO END ;GET NEXT BYTE OF DATA ;TRANSMIT THE DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT
END EMASTX
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. This can be done by setting the transmit acknowledge bit (TXAK) before reading the second last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.
8
MASR
DEC BEQ LDA DECA BNE BSET BRA BCLR LDA STA RTI
RXCNT ENMASR RXCNT
;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE TO BE ;READ ;NOT LAST ONE OR SECOND LAST ;SECOND LAST, DISABLE ;ACKNOWLEDGEMENT TRANSMITTING ;NXMAR ;LAST ONE, GENERATE STOP SIGNAL ;READ DATA AND STORE
LAMAR
NXMAR 3,MCR NXMAR 5,MCR MDR RXBUF
ENMASR NXMAR
8.5.5
Generation of a repeated START signal
At the end of the data transfer, if the master still wants to communicate on the bus, it can generate another START signal, followed by another slave address, without first generating a STOP signal. For example:
TPG
MOTOROLA 8-12
I2C-BUS
MC68HC05L28
RESTART
BCLR BSET LDAA STAA
5,MCR 5,MCR CALLING MDR
;ANOTHER START (RESTART) IS ;GENERATED BY ;THESE TWO CONSECUTIVE ;INSTRUCTIONS ;GET THE CALLING ADDRESS ;TRANSMIT THE CALLING ADDRESS
8.5.6
Slave mode
In the slave interrupt service routine, the MAAS bit should be tested to check if a calling of its own address has just been received. If MAAS is set, software should set the transmit/receive mode select bit (MTX) according to the R/W command bit, SRW. Writing to the MCR clears the MAAS bit automatically. A data transfer may then be initiated by writing to MDR or by performing a dummy read from MDR. In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. If RXAK is set, this means an `end of data' signal from the master receiver, which must then switch from transmitter mode to receiver mode by software. This is followed by a dummy read, which releases the SCL line so that the master can generate a STOP signal.
8.5.7
Arbitration lost
8
Only one master can engage the device at one time. Those devices wishing to engage the bus, but having lost arbitration, are immediately switched to slave receive mode by hardware. Their data output to the SDA line is stopped, but the internal transmitting clock is still generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with MAL = 1 and MSTA = 0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware inhibits the transmission; the MSTA bit is cleared without generating a STOP condition, an interrupt is generated, and MAL is set to indicate that the attempt to engage the bus has failed. In these cases, the slave interrupt service routine should test MAL first; if MAL is set, it should be cleared by software.
8.5.8
Operation during STOP and WAIT modes
During STOP mode, the I2C-bus is disabled. During WAIT mode, the I2C-bus is idle, but `wakes up' when it receives a valid start condition in slave mode. If the interrupt is enabled, the CPU comes out of WAIT mode after the end of a byte of transmission.
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-13
Clear MIF
Master mode?
No
A
Yes
TX
TX/ RX?
RX
Last byte transmitted?
Yes
Last byte to be read?
Yes
No
No
No
Yes
8
RXAK = 0?
Second last byte to be read?
Yes
No
Write next byte to MDR
Set TXAK = 1
Generate STOP signal
Generate STOP signal Read data from MDR and store
RTI
Figure 8-3 Example of a typical I2C-bus interrupt routine
TPG
MOTOROLA 8-14
I2C-BUS
MC68HC05L28
A
Clear MAL
Yes
Arbitration lost?
No
No
Yes
MAAS = 1? MAAS = 1?
Yes
No
Yes
SRW = 1? TX / RX?
RX
No
TX
Set TX mode
Set RX mode
Yes
ACK from receiver?
8
No
TX next byte Write to MDR Dummy read from MDR Switch to RX mode Read MDR and store
Dummy read from MDR
RTI
Figure 8-3 Example of a typical I2C-bus interrupt routine (Continued)
TPG
MC68HC05L28
I2C-BUS
MOTOROLA 8-15
8
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 8-16
I2C-BUS
MC68HC05L28
9
A/D CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation converter and a 16-channel multiplexer. There are only two A/D channels available on the MC68HC05L28. These are connected to the ADx pins of the MC68HC05L28 and the other channels are dedicated to internal reference points for test functions. The ADx pins do not have any internal output driver circuitry connected to them because this circuitry would load the analog input signal due to output buffer leakage current. There is one 8-bit result data register, ADDATA and one 8-bit status/control register, ADSTAT. The A/D converter is ratiometric and two dedicated pins, VREFH and VREFL, are used to supply the reference voltage levels of each analog input. These pins are used in preference to the system power supply lines because any voltage drops in the bonding wires of the heavily loaded supply pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than VREFH converts to $FF (full scale) with no overflow indication and an input voltage equal to VREFL converts to $00. The A/D converter can operate from either the bus clock or an internal RC type oscillator. The internal RC type oscillator is activated by the ADRC bit in ADSTAT and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too low to provide accurate results (see Section 9.2.1.2). When the A/D converter is not being used it can be disconnected, using the ADON bit in the ADSTAT register, in order to save power (see Section 9.2.1.3).
9
9.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog capacitor array, a comparator and a successive approximation register (SAR) (see Figure 9-1). There are four options that can be selected by the multiplexer; the ADx input pin, VRH, (VRH+VRL)/2 or VRL. Selection is made via the CHx bits in the ADSTAT register (see Section 9.2.1.4). ADx are the only input points for A/D conversion operations; the others are reference points which can be used for test purposes. The A/D reference input (ADx) is applied to a precision internal digital to analog converter. Control logic drives this D/A converter and the analog output is successively compared with the analog input (ADx) sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
TPG
MC68HC05L28
A/D CONVERTER
MOTOROLA 9-1
8-bit capacitive DAC with sample and hold AD0 AD1 Analog MUX (Channel assignment) Successive approximation register and control
VRH VRL
Result
VRH (VRH+VRL)/2 VRL
A/D status/control register (ADSTAT) CH0 CH1 CH2 CH3 ADON ADRC COCO
A/D result data register (ADDATA)
Figure 9-1 A/D converter block diagram
9
The result of each successive comparison is stored in the SAR and, when the conversion is complete, the contents of the SAR are transferred to the read-only result data register ($17), and the conversion complete flag, COCO, is set in the A/D status/control register ($15).
Note:
Any write to the A/D status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled.
TPG
MOTOROLA 9-2
A/D CONVERTER
MC68HC05L28
9.2 9.2.1
A/D registers A/D status/control register (ADSTAT)
Address bit 7 bit 6 bit 5 bit 4 bit 3 CH3 bit 2 CH2 bit 1 CH1 bit 0 CH0 State on reset 0000 0000
A/D status/control register (ADSTAT)
$0015 COCO ADRC ADON
9.2.1.1
1 (set)
COCO -- Conversion complete flag
- COCO flag is set each time a conversion is complete, allowing the new result to be read from the A/D result data register ($16). The converter then starts a new conversion. COCO is cleared by reading the result data register or writing to the status/control register.
0 (clear) -
Reset clears the COCO flag.
9.2.1.2
ADRC -- A/D RC oscillator control
The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds. 1 (set) - When the ADRC bit is set, the A/D RC oscillator is turned on and, if ADON is set, the A/D runs from the RC oscillator clock. See Table 9-1. When the ADRC bit is cleared, the A/D RC oscillator is turned-off and, if ADON is set, the A/D runs from the CPU clock.
9
0 (clear) -
When the A/D RC oscillator is turned on, it takes time tADRC to stabilize (see Section 12.4). During this time A/D conversion results may be inaccurate. Power-on or external reset clears the ADRC bit.
9.2.1.3
ADON -- A/D converter on
The ADON bit allows the user to enable/disable the A/D converter. 1 (set) - A/D converter is switched on. A/D converter is switched off.
0 (clear) -
When the A/D converter is switched on, it takes time tADON for the current sources to stabilize (see Section 12.4). During this time A/D conversion results may be inaccurate.
TPG
MC68HC05L28
A/D CONVERTER
MOTOROLA 9-3
Power-on or external reset will clear the ADON bit, disabling the A/D converter. Table 9-1 A/D clock selection
ADRC 0 0 1 1 ADON 0 1 0 1 RC oscillator OFF OFF ON ON A/D converter OFF ON OFF ON Comments A/D switched off. A/D using CPU clock. Allows the RC oscillator to stabilise. A/D using RC oscillator clock.
9.2.1.4
CH3 - CH0 -- A/D channels 3, 2, 1 and 0
The CH3-CH0 bits allow the user to determine which channel of the A/D converter multiplexer is selected. See Table 9-2 for channel selection. Reset clears these bits. Table 9-2 A/D channel assignment
CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel selected AD0 AD1 reserved reserved reserved reserved reserved reserved VRH pin (high) (VRH + VRL) / 2 VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low) VRL pin (low)
9
TPG
MOTOROLA 9-4
A/D CONVERTER
MC68HC05L28
9.2.2
A/D input register (ADIN)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 AD1 bit 0 AD0 State on reset Undefined
A/D input register (ADIN)
$0016
The ADIN register allows the A/D input to be read as a static input. Reading this register during an A/D conversion sequence may inject noise into the analog input and reduce the accuracy of the A/D result.
Note:
Performing a digital read of the A/D input with levels other than VDD or VSS on the ADIN pin will result in greater power dissipation during the read cycle. This will also give unpredictable results on the ADIN input.
Reset does not affect the ADIN bit.
9.2.3
A/D result data register (ADDATA)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Undefined
A/D result data register (ADDATA)
$0017
ADDATA is a read-only register which is used to store the result of an A/D conversion. The result is loaded into the register from the SAR and the conversion complete flag in the ADSTAT register, COCO, is set.
9
TPG
MC68HC05L28
A/D CONVERTER
MOTOROLA 9-5
9.3
ADx analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal capacitor through a resistive path, provided by input-selection switches and a sampling aperture time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling, the analog value is stored on the capacitor and held until the end of conversion. During this hold time, the analog input is disconnected from the internal A/D system and the external voltage source sees a high impedance input. The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance of 50 k and a capacitance of at least 10pF (these are typical values measured at room temperature).
Input protection device Analog input pin < 2pF
50k
+ ~20V - ~0.7V 400 nA junction leakage 10pF DAC capacitance V RL
9
Note:
The analog switch is closed during the 12 cycle sample time only.
Figure 9-2 Electrical model of an A/D input pin
TPG
MOTOROLA 9-6
A/D CONVERTER
MC68HC05L28
10
RESETS AND INTERRUPTS
10.1 Resets
The MC68HC05L28 can be reset in three ways: by the initial power-on reset function, by an active low input to the RESET pin and by a COP watchdog timer reset, if the watchdog timer is enabled.
10.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the oscillator becomes active. If the external RESET pin is low at the end of this delay then the processor remains in the reset state until RESET goes high. The user must ensure that the voltage on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed. If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached the specified minimum operating voltage. This may be accomplished by connecting an external RC-circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great enough (at least 100ms) to allow the oscillator circuit to stabilise.
10
10.1.2
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (tCYC). This pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
TPG
MC68HC05L28
RESETS AND INTERRUPTS
MOTOROLA 10-1
10.1.3
Computer operating properly (COP) reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence.
Note:
COP timeout is prevented by periodically writing a `0' to bit 0 of address $3FF0.
If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU. Because the internal reset signal is used, the MCU comes out of a COP reset in the same operating mode it was in when the COP timeout was generated. The COP reset function is enabled or disabled by a bit in the option register. See Section 5.2 for more information on the COP watchdog timer.
10.2
Interrupts
The MCU can be interrupted by different sources - six maskable hardware interrupts and one non-maskable software interrupt: * * * * * External signal on the IRQ pins (IRQ0, IRQ1, IRQ2) Core timer 16-bit programmable timer I2C Software Interrupt Instruction (SWI)
10
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 10-1 shows the relative priority of all the possible interrupt sources. Figure 10-1 shows the interrupt processing flow.
TPG
MOTOROLA 10-2
RESETS AND INTERRUPTS
MC68HC05L28
Table 10-1 Interrupt priorities
Source Reset Software interrupt (SWI) External interrupt (IRQ) Core timer I2C Programmable timer Register -- -- IRQx CTCSR MSR TSR Flags -- -- IRQxINT CTOF, RTIF MIF ICF, OCF, TOF Vector Address $3FFE, $3FFF $3FFC, $3FFD $3FFA, $3FFB $3FF8, $3FF9 $3FF6, $3FF7 $3FF4, $3FF5 Priority highest
lowest
10.2.1
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
10.2.2
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared.
10
TPG
MC68HC05L28
RESETS AND INTERRUPTS
MOTOROLA 10-3
From RESET
Yes Is I-bit set?
No IRQ0,1,2 External interrupt? No Core timer interrupt? Yes Yes Clear IRQ0,1,2
Stack PC, X, A, CC
No I2C interrupt? Yes
Set I-bit
Load PC From: No TIMER16 interrupt? No Fetch next instruction Yes SWI: IRQ0: IRQ1: IRQ2: CTimer: I2C: TIM16: $3FFC - $3FFD $3FFA - $3FFB $3FFA - $3FFB $3FFA - $3FFB $3FF8 - $3FF9 $3FF6 - $3FF7 $3FF4 - $3FF5
10
SWI instruction ? No RTI instruction ? No Execute instruction Yes Restore registers from stack: CC, A, X, PC Yes
Figure 10-1 Interrupt flow chart
TPG
MOTOROLA 10-4
RESETS AND INTERRUPTS
MC68HC05L28
10.2.2.1
External interrupt (IRQ0, IRQ1, IRQ2)
These external interrupt sources use the same interrupt vector ($3FFA, $3FFB) IRQ0 If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I-bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ0. It is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $3FFA and $3FFB. Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger can be selected by bit-1 (IRQED) in the option register ($1D). When IRQED is cleared, the interrupt is edge-and-level sensitive and when set the interrupt is edge sensitive. IRQED can be written to once only after a power-on-reset or external reset. This bit is cleared after reset. IRQ1
Address IRQ1 status/control register (IRQ1) $000A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset ??00 0000
IRQ1INT IRQ1ENA IRQ1LV IRQ1EDGIRQ1RSTIRQ1VAL
This interrupt can be enabled independently and different sensitivities can be defined: falling edge, falling edge and low level, rising edge, rising edge and high level. The interrupt is enabled by setting bit 4 (IRQ1ENA) of register $0A and is disabled by clearing it. The interrupt vector, $3FFA and $3FFB, is shared with the other IRQ interrupts. Bit 5 of register $0A is an interrupt flag (IRQ1INT) which distinguishes between the interrupts and is set when an interrupt occurs. The interrupt is cleared by writing 1 to the IRQ1RST bit which always reads 0. The status of IRQ1 can be monitored by reading the IRQ1VAL bit (bit 0 on the IRQ1 register). IRQ1INT -- IRQ1 interrupt flag 1 (set) - A valid IRQ1 interrupt has been generated. No valid IRQ1 interrupt has been generated.
10
0 (clear) -
IRQ1ENA -- IRQ1 interrupt enable 1 (set) - IRQ1 interrupts are enabled. IRQ1 interrupts are disabled.
0 (clear) -
IRQ1LV, IRQ1EDG -- IRQ1 interrupt sensitivity bits These two bits are used to select the sensitivity of the IRQ1 interrupt trigger according to Table 10-2.
TPG
MC68HC05L28
RESETS AND INTERRUPTS
MOTOROLA 10-5
Table 10-2 IRQ1 interrupt sensitivity IRQ1LV 0 0 1 1 IRQ1RST -- IRQ1 reset The IRQ1 interrupt is cleared by writing a `1' to this bit. This bit is write-only and always returns zero. IRQ1VAL -- IRQ1 pin status The IRQ1VAL bit reflects current status of the IRQ1 pin. IRQ2
Address IRQ2 status/control register (IRQ2) $000B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset ??00 0000
IRQ1EDG 0 1 0 1
Interrupt sensitivity Falling edge Rising edge Falling edge and low level Rising edge and high level
IRQ2INT IRQ2ENA IRQ2LV IRQ2EDGIRQ2RSTIRQ2VAL
10
This interrupt can be enabled independently and different sensitivities can be defined: falling edge, falling edge and low level, rising edge, rising edge and high level. The interrupt is enabled by setting bit 4 (IRQ2ENA) of register $0B and is disabled by clearing it. The interrupt vector, $3FFA and $3FFB, s shared with the other IRQ interrupts. Bit 5 of register $0B is an interrupt flag (IRQ2INT) which distinguishes between the interrupts and is set when an interrupt occurs. The interrupt is cleared by writing 1 to the IRQ2RST bit which always reads 0. The status of IRQ2 can be monitored by reading the IRQ2VAL bit (bit 0 on the IRQ2 register). IRQ2INT -- IRQ2 interrupt flag 1 (set) - A valid IRQ2 interrupt has been generated. No valid IRQ2 interrupt has been generated.
0 (clear) -
IRQ2ENA -- IRQ2 interrupt enable 1 (set) - IRQ2 interrupts are enabled. IRQ2 interrupts are disabled.
0 (clear) -
IRQ2LV, IRQ2EDG -- IRQ2 interrupt sensitivity bits These two bits are used to select the sensitivity of the IRQ2 interrupt trigger according to Table 10-2.
TPG
MOTOROLA 10-6
RESETS AND INTERRUPTS
MC68HC05L28
Table 10-3 IRQ2 interrupt sensitivity IRQ2LV 0 0 1 1 IRQ2RST -- IRQ2 reset The IRQ2 interrupt is cleared by writing a `1' to this bit. This bit is write-only and always returns zero. IRQ2VAL -- IRQ2 pin status The IRQ2VAL bit reflects current status of the IRQ2 pin. IRQ2EDG 0 1 0 1 Interrupt sensitivity Falling edge Rising edge Falling edge and low level Rising edge and high level
10.2.2.2
Real time and core timer (CTIMER) interrupts
There are two core timer interrupt flags that cause a CTIMER interrupt whenever an interrupt is enabled and its flag becomes set (RTIF and CTOF). The interrupt flags and enable bits are located in the CTIMER control and status register (CTCSR). These interrupts vector to the same interrupt service routine, whose start address is contained in memory locations $3FF8 and $3FF9 (see Section 5.3.1 and Figure 5-1). To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set after the specified number of counts. To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will then be set when the core timer counter register overflows from $FF to $00.
10
10.2.2.3
Programmable 16-bit timer interrupt
There are five interrupt flags that cause a timer interrupt when set and enabled. The timer interrupt enable bits are located in the timer control registers (TCR) and the timer interrupt flags are located in the timer status registers (TSR). All interrupts vector to the same service routine, whose start address is contained in memory locations $3FF4 and $3FF5. In WAIT mode the CPU clock halts but the timer continues to run.
TPG
MC68HC05L28
RESETS AND INTERRUPTS
MOTOROLA 10-7
10.2.2.4
I2C interrupts
There is an interrupt flag and three status flags for the I2C that cause an I2C interrupt when set and enabled. These interrupts will vector to the service routine located at the address specified by the contents of memory locations $3FF6 and $3FF7.
10.2.3
Hardware controlled interrupt sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Section 2-5 and Figure 2-6. RESET: A reset condition causes the program to vector to its starting address, which is contained in memory locations $3FFE (MSB) and $3FFF (LSB). The I-bit in the condition code register is also set, to disable maskable interrupts. The STOP instruction causes the oscillator to be turned off and the processor to `sleep' until an external interrupt (IRQ) interrupt occurs, or the device is reset. The WAIT instruction causes all processor clocks to stop, but leaves the core timer clock running. This `rest' state of the processor can be cleared by reset, an external interrupt (IRQ), or a timer interrupt. There are no special WAIT vectors for these interrupts.
STOP: WAIT:
10
TPG
MOTOROLA 10-8
RESETS AND INTERRUPTS
MC68HC05L28
11
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05L28.
11.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 11-1. The interrupt stacking order is shown in Figure 11-2.
7 7 15 7 00 15 7 0000000011 7 111HINZ 0 Accumulator 0 Index register 0 Program counter 0 Stack pointer 0 C Condition code register Carry / borrow Zero Negative Interrupt mask Half carry
11
Figure 11-1 Programming model
11.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-1
7 Increasing memory address Condition code register Accumulator Index register Program counter high Program counter low Return
0
Stack Interrupt Decreasing memory address
Unstack
Figure 11-2 Stacking order
11.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area.
11.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched. Although the M68HC05 CPU core can address 64K bytes of memory, the actual address range of the MC68HC05L28 is limited to 16K bytes. The two most significant bits of the program counter are therefore not used and are permanently set to zero.
11.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack.
11
When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
11.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
TPG
MOTOROLA 11-2
CPU CORE AND INSTRUCTION SET
MC68HC05L28
Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
11.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control
11
The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 11-1.
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-3
11.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 11-2 for a complete list of register/memory instructions.
11.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 11-3.
11.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 11-4.
11.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 11-5 for a complete list of read/modify/write instructions.
11
11.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 11-6 for a complete list of control instructions.
11.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 11-8).
TPG
MOTOROLA 11-4
CPU CORE AND INSTRUCTION SET
MC68HC05L28
Table 11-1 MUL instruction
Operation Description X:A X*A Multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared MUL Addressing mode Cycles Bytes Opcode Inherent 11 1 $42
Condition codes Source Form
Table 11-2 Register/memory instructions
Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles 5 5 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 4 7 6 6 Opcode D6 DE 5 5 4 4 4 4 4 4 4 4 4 4 3 6 D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD 3 3 # Bytes
# Cycles
# Cycles
Opcode
Opcode
Opcode C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD
# Bytes
# Bytes
Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine
LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR
A6 AE
2 2
2 2
B6 BE B7 BF
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Bytes
4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4
AB A9 A0 A2 A4 AA A8 A1 A3 A5
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD
11
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-5
Table 11-3 Branch instructions
Relative addressing mode Opcode # Bytes # Cycles 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 24 2 3 25 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 2A 2 3 2B 2 3 2C 2 3 2D 2 3 2E 2 3 2F 2 3 AD 2 6
Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine
Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR
Table 11-4 Bit manipulation instructions
Addressing modes Bit set/clear Bit test and branch Opcode # Bytes # Cycles Opcode # Bytes # Cycles 2*n 3 5 01+2*n 3 5 10+2*n 2 5 11+2*n 2 5
Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n
Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7)
11
TPG
MOTOROLA 11-6
CPU CORE AND INSTRUCTION SET
MC68HC05L28
Table 11-5 Read/modify/write instructions
Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes
# Bytes
# Bytes
Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply
INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL
4C 4A 4F 43 40 49 46 48 44 47 4D 42
1 3 5C 1 3 5A 1 3 5F 1 3 53 1 3 50 1 3 59 1 3 56 1 3 58 1 3 54 1 3 57 1 3 5D 1 11
1 3 3C 1 3 3A 1 3 3F 1 3 33 1 3 30 1 3 39 1 3 36 1 3 38 1 3 34 1 3 37 1 3 3D
2 5 7C 2 5 7A 2 5 7F 2 5 73 2 5 70 2 5 79 2 5 76 2 5 78 2 5 74 2 5 77 2 4 7D
# Bytes
1 5 6C 1 5 6A 1 5 6F 1 5 63 1 5 60 1 5 69 1 5 66 1 5 68 1 5 64 1 5 67 1 4 6D
26 26 26 26 26 26 26 26 26 26 25
Table 11-6 Control instructions
Inherent addressing mode Opcode # Bytes # Cycles 97 1 2 9F 1 2 99 1 2 98 1 2 9B 1 2 9A 1 2 83 1 10 81 1 6 80 1 9 9C 1 2 9D 1 2 8E 1 2 8F 1 2
Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait
Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT
11
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-7
Table 11-7 Instruction set
Addressing modes EXT REL IX IX1 Condition codes I NZC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * 01 * *
Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP
INH
IMM
DIR
IX2
BSC BTB
H
11
* * * * * * * * * * * * * * * * * * * * * * * 0 * *
Address mode abbreviations
BSC Bit set/clear BTB Bit test & branch DIR INH Direct Inherent EXT Extended IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
TPG
MOTOROLA 11-8
CPU CORE AND INSTRUCTION SET
MC68HC05L28
Table 11-7 Instruction set (Continued)
Addressing modes EXT REL IX IX1 Condition codes I NZC * * 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 * * * 0 * * * * * * * * * * * * * * * * * * * ????? * * * * * * * * * * * 1 * 1 * * * * * * * 0 * * * * * * * * * 1 * * * * * * * * * * * * * * * * * 0 * * *
Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT
INH
IMM
DIR
IX2
BSC BTB
H
11
Address mode abbreviations
BSC Bit set/clear BTB Bit test & branch DIR INH Direct Inherent EXT Extended IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-9
11
Control
High
MOTOROLA 11-10
DIR 3 0011 Low
3 IX 3 3
High NEG
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
Low
Bit manipulation BTB BSC 0 1 0000 0001 INH 4 0100 NEGA RTS
1 INH 2 INH 6 2 3
Branch REL 2 0010 IX 7 0111
6
Read/modify/write INH IX1 5 6 0101 0110 INH 8 1000
5
INH 9 1001
9
IMM A 1010 SUB CMP SBC
2 IMM 2 2 IMM 2 2 2
DIR B 1011 SUB CMP SBC CPX AND BIT LDA STA
2 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 3
Register/memor y EXT IX2 C D 1100 1101 IX1 E 1110
5
IX F 1111
4
BRSET0
REL 2 3
5
BSET0 CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP
2 DIR 3 3 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4
5
BRA CMP SBC CPX AND BIT LDA STA EOR
EXT 3 4 EXT 3 4 EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5
NEGX CMP SBC CPX AND BIT
IX2 2 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4
3
NEG CMP SBC CPX AND BIT LDA
IX2 2 6 IX1 1 4
NEG
RTI
SUB
4
SUB
SUB
SUB
3
BRCLR0
REL 3
BTB 2 5
BCLR0 MUL
1 11 REL 3
BSC 2 5 IX 3
BRN
3
BRSET1 COM LSR
DIR 1 INH 1 INH 2 IX1 1 IX 2 DIR 1 5 5
BTB 2 5 INH 3
BSET1 COMA LSRA BIT
2 IMM 2 2 INH 1 3
BSC 2 5
BHI COMX LSRX
INH 2 3 3
3
BRCLR1
REL 2 3
BTB 2 5
BCLR1 LSR
IX1 1 6
BSC 2 5
BLS LSR
IX 1 5 INH 2
COM AND
IMM 2 2
6
COM
5
SWI
10
CPX
IMM 2 2
IX 3 IX 3 IX 3
3
BRSET2
REL 2 3 REL 3
BTB 2 5
BSET2
BSC 2 5
BCC
3
BRCLR2 ROR ASR LSL ROL DEC
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5
BTB 2 5
BCLR2 RORA ASRA LSLA ROLA DECA SEI
1 INH 2 2 INH 1 3 INH 1 3 INH 1 3 INH 1 3 3
BSC 2 5
BCS RORX ASRX LSLX ROLX DECX ADD
IMM 2 2 IMM 2 INH 2 3 INH 2 3 INH 2 3 INH 2 3 3
3
BRSET3
REL 2 3
BTB 2 5
BSET3 ASR LSL ROL DEC
IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6
BSC 2 5
BNE ASR LSL ROL DEC
IX 5 1 IX 5 1 IX 5 1 IX 5 2 IMM 2
ROR TAX CLC SEC CLI
INH 2 2 INH 2 2 INH 2 2
6
ROR
5
LDA
IMM 2 2
LDA STA
IX2 2 5 IX2 2 5 IX1 1 5
IX 3 IX 4
3
BRCLR3
REL 2 3
BTB 2 5
BCLR3 EOR ADC ORA
IMM 2 2 IMM 2 2 2
BSC 2 5 DIR 3 3 DIR 3 3 DIR 3 3 EXT 3 4
BEQ EOR ADC ORA
REL 2 3
STA EOR ADC ORA ADC
IX2 2 5 IX2 2 5 IX1 1 4 IX1 1 4 IX1 1 4
3
BRSET4
REL 2 3 REL 2 3 REL 3
BTB 2 5
BSET4
BSC 2 5
BHCC
EOR ADC ORA ADD ADD ADD ORA
IX1 1 4
IX 3 IX 3 IX 3 IX 3
3
BRCLR4
BTB 2 5
BCLR4
BSC 2 5
BHCS
3
BRSET5
BTB 2 5
BSET5
BSC 2 5
BPL
3
BRCLR5 INC TST
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 4 5
BTB 2 5
BCLR5 INCA TSTA STOP
1 2 2 INH 1 3 3
BSC 2 5
BMI INCX TSTX
INH 2 3 3
ADD
DIR 3 2
3
BRSET6
REL 2 3
BTB 2 5
BSET6 TST
IX1 1 5
BSC 2 5
BMC TST
IX 4 1
INC NOP
INH 2 INH 2
6
INC
5
RSP
INH 2 2
JMP BSR LDX
6 REL 2 2 IMM 2
EXT 3 3 DIR 3 5 EXT 3 6
JMP JSR LDX JSR
DIR 3 3
IX2 2 4 IX2 2 7
JMP JSR LDX
EXT 3 4
IX1 1 3 IX1 1 6
JMP JSR LDX
IX2 2 5
IX 2 IX 5
3
BRCLR6
REL 2 3 REL 3
BTB 2 5
BCLR6
BSC 2 5
BMS
JSR LDX
IX1 1 4
3
BRSET7 CLR
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
BTB 2 5
BSET7 CLRA
3
BSC 2 5
BIL CLRX
3
LDX TXA
2 INH 2
IX 3
Table 11-8 M68HC05 opcode map
3
CPU CORE AND INSTRUCTION SET
CLR
6
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 CLR
5
BRCLR7
REL 2
BTB 2 5
BCLR7
BSC 2 5
BIH
WAIT
INH 2 INH 1
STX
DIR 3 4 DIR 3
STX
EXT 3 5 EXT 3
STX
IX2 2 6 IX2 2
STX
IX1 1 5 IX1 1
STX
IX 4 IX
3
BTB 2
BSC 2
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for address modes and register s
Legend F 1111 Mnemonic
1
Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles Address mode
3 IX
BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accum ulator Index register
Bit set/clear Bit test and branch Direct Extended Inherent Immediate
MC68HC05L28
0 0000
TPG
11.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide.
11.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long.
11.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2
11
11.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
TPG
MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-11
11.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2)
11.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X
11.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1)
11
11.3.7 Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2)
TPG
MOTOROLA 11-12
CPU CORE AND INSTRUCTION SET
MC68HC05L28
11.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2
11.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
11.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3
11
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MC68HC05L28
CPU CORE AND INSTRUCTION SET
MOTOROLA 11-13
THIS PAGE LEFT BLANK INTENTIONALLY
11
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MOTOROLA 11-14
CPU CORE AND INSTRUCTION SET
MC68HC05L28
12
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the MC68HC05L28.
12.1
Maximum ratings
Table 12-1 Maximum ratings
Rating Supply voltage(1) Input voltage: Normal operations Bootloader mode (IRQ0 pin only) Current sink into port B Operating temperature range MC68HC05L28 (standard) Storage temperature range Current drain per pin(2) - excluding VDD and VSS (1) All voltages are with respect to V . SS (2) Maximum current drain per pin is for one pin at a time, limited by an external resistor. Symbol V DD V IN Value - 0.3 to +7.0 V SS - 0.3 to VDD + 0.3 V SS - 0.3 to 2xVDD + 0.3 80 TL to TH -40 to +85 - 65 to +150 25 Unit V V mA C C mA
IB TA T STG ID
Note:
This device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. For maximum reliability all unused inputs should be tied to either VSS or VDD.
12
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MC68HC05L28
ELECTRICAL SPECIFICATIONS
MOTOROLA 12-1
12.2
Thermal characteristics and power considerations
Table 12-2 Package thermal characteristics
Characteristics Thermal Resistance - Plastic 56-pin SDIP Symbol JA Value TBD Unit C/W
The average chip junction temperature, TJ, in degrees Celcius can be obtained from the following equation: T J = T A + ( P D * JA ) where: TA = Ambient Temperature (C) JA = Package Thermal Resistance, Junction-to-ambient (C/W) PD = PINT + PI/O (W) PINT = Internal Chip Power = IDD * VDD (W) PI/O = Power Dissipation on Input and Output pins (User determined) An approximate relationship between PD and TJ (if PI/O is neglected) is: K P D = --------------------T J + 273 Solving equations [1] and [2] for K gives: K = P D * ( T A + 273 ) + JA * P D2 [3] [2] [1]
where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA by solving the above equations. The package thermal characteristics are shown in Table 12-2.
V DD = 4.5 V R2 Pins PA0-7, PB0-7 R1 3.26k R2 2.38k C 50pF Test Point C R1
12
Figure 12-1 Equivalent test load
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MOTOROLA 12-2
ELECTRICAL SPECIFICATIONS
MC68HC05L28
12.3
DC electrical characteristics for 5V operation
Table 12-3 DC electrical characteristics
(VDD = 5.0 Vdc 10%, V SS = 0 Vdc, TA = -40C to +85C, unless otherwise stated) Characteristic Symbol Min Typ (1) Output voltage ILOAD = - 10 A VOH V DD - 0.1 -- ILOAD = +10 A VOL -- -- Output high voltage (ILOAD = - 0.8 mA) VOH V DD - 0.8 -- PA, PB, PD Output low voltage (ILOAD = +1.6 mA) VOL -- -- PA, PB, PD Input high voltage V IH 0.7xV DD -- PA, PB, PD, OSC1, IRQ (2), RESET Input low voltage V IL V SS -- PA, PB, PD, OSC1, IRQ (2), RESET Port D pull-up value 50 Supply current(3) RUN -- WAIT IDD -- STOP (25 C) -- STOP (0 C) -- I/O ports I/P leakage (PA, PB, PD) V IN = VSS IIL -10 -- V IN = VDD IIH -- -- Input current (RESET, IRQ(2), OSC1) IIL -1 -- V IN = VSS V IN = VDD IIH -- -- Capacitance (4) Ports (input or output) C OUT -- -- RESET, IRQ (2) C IN -- -- Hysteresis(4) RESET, IRQ (2), TCAP1, TCAP2 V HYS -- 0.6 OSC2 DRIVE VOSCH IL = - 0.2 mA V DD - 0.08 -- VOSCL IL = 0.2 mA -- --
Max -- 0.1 -- 0.4
Unit V V V V V V k
25 10 100 100 -- 10 -- 1 12 8 -- -- 0.08
mA mA A A A A A A pF pF V V
(1) Typical values are at mid point of voltage range and at 25 only. All values shown reflect average C measurements. (2) IRQ denotes IRQ0 - 2. (3) Wait IDD : Timer, I2C-bus systems active. RUN and WAIT I DD : measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2). STOP and WAIT I DD : all ports configured as inputs; V = 0.2 V and VIH = VDD - 0.2 V. IL STOP I DD : measured with OSC1 = V SS . WAIT IDD is affected linearly by the OSC2 capacitance. (4) Values are guaranteed, but not tested.
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MC68HC05L28
ELECTRICAL SPECIFICATIONS
MOTOROLA 12-3
12.4
AC electrical characteristics for 5V operation
Table 12-4 Control timing
Characteristics Frequency of operation crystal external clock Internal operating frequency crystal external clock Cycle time Crystal oscillator start-up time Stop recovery start-up time (crystal oscillator) RESET pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(1) OSC1 pulse width EEPROM byte erase time (0 - 70 C) EEPROM block erase time (0 - 70 C) EEPROM bulk erase time (0 - 70 C) EEPROM bulk erase time (0 - 70 C) EEPROM bulk erase time (0 - 70 C) 16 bit timer resolution(2) 16 bit timer input capture pulse width 16 bit timer input capture pulse period Symbol fOSC fOSC fOP fOP tCYC t OXOV t ILCH t RL t ILIH tILIL t OH , tOL tEBYT tEBLK tEBULF tEBYT tFPV tRESL t TLTH t TLTL Min -- dc -- dc 460 -- -- 1.5 250 -- 90 10 100 400 10 -- 4 250
(3)
Max 4.332 4.332 2.17 2.17 -- 100 100 -- -- -- -- -- -- -- -- 10 5 -- --
Unit MHz MHz MHz MHz ns ms ms t CYC ns t CYC ns ms ms ms ms s tCYC ns t CYC
(1) The minimum period t ILIL should not be less than the number of cycle times it takes to execute service routine plus 21 tCYC (2) Since a 2-bit prescaler in the timer must count four external cycles CYC ) this is the limiting factor in determining (t the timer resolution (3) The minimum period t TLTL should not be less than the number of cycles it takes to execute the interrupt service routine plus 24 tCYC
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MOTOROLA 12-4
ELECTRICAL SPECIFICATIONS
MC68HC05L28
12.5
A/D converter characteristics
Table 12-5 A/D converter characteristics
Characteristics Resolution Absolute Accuracy (1) Conversion Range (2) V REFH V REFL Power up time Input leakage AD5 - AD0 Pin under test = VSS - 0.3V Pin under test = VDD+0.3V Conversion time Monotonicity(4) Zero input reading (VIN = 0V) Ratiometric reading (VIN = VREF ) Sample time Input capacitance Analog input voltage (1) This figure includes quantization noise (2) A/D accuracy may decrease proportionally as VREFH is reduced below 4.0V (3) TAD = T CYC if the clock source is the same as the MCU (4) Inherently guaranteed by the design Min 8 -- V SS - 0.1 V REFL - 0.1 -- -1 -- 32 00 FF 12 -- VREFL Max 8 1.5 VDD + 0.1 V REFH VREFH 100 -- 1 32 01 FF 12 8 V REFH Units Bits LSB V V V ms A A TAD (3) Hex Hex TAD (3) pF V
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ELECTRICAL SPECIFICATIONS
MOTOROLA 12-5
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MOTOROLA 12-6
ELECTRICAL SPECIFICATIONS
MC68HC05L28
13
MECHANICAL DATA
13.1 Pin configurations -- 56-pin SDIP
VSS VDD IRQ2 IRQ1 VPP /IRQ0 RESET OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11
1 2 3 4 5 6 7 8
56 55 54 53 52 51 50 49
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VREFH AD1 AD0 VREFL PDO/TCAP1 PD1/TCMP1 PD2/TCAP2 PD3/TCMP2 PD4/SDA0 PD5/SCLO BP3 BP2 BP1 BP0 FP17 FP16 FP15 FP14 FP13 FP12
MC68HC05L28/MC68HC705L28
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
13
Figure 13-1 56-pin SDIP pinout for the MC68HC05L28/MC68HC705L28
TPG
MC68HC05L28
MECHANICAL DATA
MOTOROLA 13-1
13.2
Mechanical dimensions -- 56-pin plastic shrink dual-in-line (SDIP)
E E1
56
29
Case No. TBD 56 lead SDIP
1 28 o Q1 Q2 D A Base Plane B1 B e1 S A1 L Seating Plane C eA
Dim. A A1 B B1 C D E E1
Min. - 0.51 0.38 0.76 0.20 57.40 19.05 16.76
Max. 5.08 - 0.56 1.27 0.30 57.91 19.69 17.27
Notes
Dimensions and tolerancing per ANSI Y 14.5 1982. Controlling dimension is mm. o applies to spread leads prior to installation. Dimensions D and E 1 are to be measured at maximum material condition but do not include mould flash. Allowable mould flash is 0.254 mm. 5. Dimensions A, A1 and L are measured with the package seated in Jedec seating plane gauge GS-3. 6. This package conforms to EIAJ reference SC-553-64B. 1. 2. 3. 4.
Dim. e1 eA L o Q1 Q2 S
Min. Max. 1.78 BSC 19.05 BSC 3.05 3.43 0 15 1.65 1.91 3.81 1.19 1.45
Figure 13-2 Mechanical dimensions for 56-pin SDIP
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MOTOROLA 13-2
MECHANICAL DATA
MC68HC05L28
14
ORDERING INFORMATION
This section describes the information needed to order the MC68HC05L28 or MC68HC705L28. To initiate a ROM pattern for the MCU, it is necessary to contact your local field service office, local sales person or Motorola representative. Please note that you will need to supply details such as: mask option selections, temperature range, oscillator frequency, package type, electrical test requirements and device marking details so that an order can be processed, and a customer specific part number allocated. Refer to Table 14-1 for appropriate part numbers.
Table 14-1 MC order numbers
Device title MC68HC05L28 MC68HC705L28 Package type 56-pin SDIP 56-pin SDIP (OTP) Temperature Part number 0 to +70C MC68HC05L28B 0 to +70C MC68HC705L28B
14.1
EPROM
A 16K byte EPROM programmed with the customer's software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
14.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process.
14
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MC68HC05L28
ORDERING INFORMATION
MOTOROLA 14-1
14.3
ROM verification units (RVU)
Ten MCUs containing the customer's ROM pattern will be provided for program verification. These units will have been made using the custom mask but are for ROM verification only. For expediency, they are usually unmarked and are tested only at room temperature (25C) and at 5 Volts. These RVUs are included in the mask charge and are not production parts. They are neither backed nor guaranteed by Motorola Quality Assurance.
14
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MOTOROLA 14-2
ORDERING INFORMATION
MC68HC05L28
A
MC68HC705L28
This appendix summarises the differences between the MC68HC05L28 and the MC68HC705L28. The same information can also be found in appropriate sections of the book. The MC68HC705L28 is an EPROM version of the MC68HC05L28. The 8176 bytes of user ROM in the MC68HC05L28 are replaced by 8128 bytes of user EPROM.
A.1
* * *
Features
8128 bytes of user EPROM RAM bootloader is different to the RAM bootloader in the MC68HC05L28 EPROM bootloader mode
A.2
Modes of operation
The MC68HC705L28 also has two modes of operation - single chip and EPROM/RAM bootloader. Table A-1 shows the conditions required to enter each mode on the rising edge of RESET. Table A-1 MC68HC705L28 operating mode entry conditions
IRQ0/VPP V SS to VDD V TST V TST V TST V TST PB2 x 0 0 1 1 PB3 x 0 1 0 1 PB6 x V DD V DD V DD V DD Mode Single chip EPROM bootloader RAM bootloader Verify only Program/verify Jump to RAM ($81) Load/execute RAM
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MC68HC05L28
MC68HC705L28
MOTOROLA A-1
15
A.2.1
Single chip mode
This is the normal operating mode of the MC68HC705L28. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including two 8-bit I/O ports and one 6-bit I/O port, available to the user. All address and data activity occurs within the MCU. Single chip mode is entered on the rising edge of RESET if the voltage level on the IRQ0 pin is within the normal operating range. Warning: In the MC68HC705L28, all vectors are fetched from EPROM in single chip mode; therefore, the EPROM must be programmed (via the bootloader mode) before the device is powered up in single chip mode.
A.2.2
EPROM bootloader mode
This mode is used for programming the on-board EPROM. In bootloader mode the operation of the device is the same as in single chip mode, except that the vectors are fetched from a reserved area of ROM at locations $3FE4 to $3FEF, instead of the EPROM. The pin assignments are identical to that of single chip mode shown earlier. A recommended programming circuit is shown in Figure A-1. Because the addresses in the MC68HC705L28 and the EPROM containing the user code are incremented independently, it is essential that the data layout in the 27128 EPROM conforms exactly to the MC68HC705L28 memory map. The bootloader uses an external 14-bit counter to address the memory device containing the code to be copied. This counter requires a clock and a reset function which are provided by the MC68HC705L28. In this mode all interrupt vectors are mapped to pseudo-vectors in RAM (see Table A-2). This allows programmers to use their own service routine addresses. Each pseudo-vector is allowed three bytes of space, rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service routine address. The bootloader code deals with the copying of user code from an external EPROM into the on-chip EPROM. The bootloader function can only be used with an external EPROM. The bootloader performs a programming pass followed by a verify pass. Pins PB2 and PB3 are used to select various bootloader functions, including the programming mode (see Figure A-1). Two other pins, PB1 and PB6 are used to drive the PROG and VERF LED outputs. While the EPROM is being programmed the PROG LED lights up; when programming is complete the internal EPROM contents are compared to that of the external EPROM and, if they match exactly, the VERF LED lights up. When finished programming, the PROG LEG turns off. If the MC68HC705L28 memory contents are the same as the EPROM the VERF LED lights up, otherwise no LEDs are turned on.
15
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MOTOROLA A-2
MC68HC705L28
MC68HC05L28
Note:
The EPROM must be erased before performing a program cycle.
L1 = VERIFY L2 = PROGRAM
S1 1 0
S2 0 0
Function Program/verify Verify only
+5V
L1
+5V
L2
+5V +5V
10K 10K
470
470
PB6
PB1
PB7 PB5
clock clear
+5V
+5V RESET
10K 10K S3
+5V
VDD TCAP1 TCAP2 VREFH
+5V +5V VCC VPP PGM
PB2
S2
RST Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
CLK
MC68HC705L28
PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D0 D1 D2 D3 D4 D5 D6 D7
MCM 27128 (16K EPR OM)
S1
VREFL ADIN
VPP
IRQ0/VPP OE VSS OCS1 OCS2 VSS CE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
VDD
MC74HC393 VSS
10 M 4 MHz 22pF 22pF
Figure A-1 MC68HC705L28 EPROM programming circuit
TPG
MC68HC05L28
MC68HC705L28
MOTOROLA A-3
15
A.2.3
RAM bootloader mode
In addition to the EPROM bootloader mode on the MC68HC705L28, there is a RAM bootloader mode that allows the user to perform simple load and execute instructions in ROM. To make use of this feature a circuit board should be constructed as shown in Figure A-1. In the RAM bootloader mode all interrupt vectors are mapped to pseudo-vectors in RAM (see Table A-2). This allows programmers to use their own service routine addresses. Each pseudo-vector is allowed three bytes of space, rather than the two bytes for normal vectors, because an explicit jump (JMP) opcode is needed to cause the desired jump to the user's service routine address.
Table A-2 MC68HC705L28 bootloader mode jump vectors
Address 0083 0086 0089 008C 008F Pseudo-vector Software interrupt IRQ Core timer I 2C-bus 16 bit timer
A.3
VPP
The VPP pin is the voltage input for the EPROM in both read and programming modes.
15
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MOTOROLA A-4
MC68HC705L28
MC68HC05L28
A.4
EPROM programming register (PCR)
Address EPROM program (PCR) $001C bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ELAT bit 0 State on reset
PGM uuuu uu0u
A.4.1
1 (set)
ELAT -- EPROM latch control
- When this bit is set to 1, the EPROM address and data buses are configured for programming. This causes the address and data buses to be latched when a write to EPROM is executed. The EPROM cannot be read if it is set to 1. The EPROM address and data buses are configured for normal reads.
0 (clear) -
A.4.2
1 (set)
PGM -- EPROM program control
- Programming power is connected to the EPROM array. The PGM can only be set if ELAT is set and it is automatically cleared when ELAT = 0. EPROM address and data bus are configured for normal reads.
0 (clear) -
Note:
ELAT and PGM cannot be set in the same write operation.
Take the following steps to program a byte of EPROM: - - - - - Apply the programming voltage VPP to the VPP pin. Set the ELAT bit. Write to the EPROM address. Set the PGM bit for a time tPROG to apply the programming voltage. Clear the ELAT and PGM bits. The erased state of the EPROM is $00.
Note:
TPG
MC68HC05L28
MC68HC705L28
MOTOROLA A-5
15
A.5
Pin configurations -- 56-pin SDIP
VSS VDD IRQ2 IRQ1 IRQ0/VPP RESET OSC1 OSC2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11
1 2 3 4 5 6 7 8 9 10
56 55 54 53 52 51 50 49 48 47
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VREFH AD1 AD0 VREFL PDO/TCAP1 PD1/TCMP1 PD2/TCAP2 PD3/TCMP2 PD4/SDA0 PD5/SCLO BP3 BP2 BP1 BP0 FP17 FP16 FP15 FP14 FP13 FP12
MC68HC705L28
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Figure A-2 56-pin SDIP pinout for the MC68HC705L28
A.6
Ordering information
A 16K byte EPROM programmed with the customer's software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed. Table A-3 MC68HC705L28 order numbers
Device title MC68HC705L28 Package type 56-pin SDIP (OTP) Temperature Part number 0 to +70C MC68HC705L28B
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MOTOROLA A-6
MC68HC705L28
MC68HC05L28
GLOSSARY
This section contains abbreviations and specialist words used in this data sheet and throughout the industry. Further information on many of the terms may be gleaned from Motorola's M68HC11 Reference Manual, M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx %xxxx A/D, ADC Bootstrap mode Byte CCR CERQUAD Clear CMOS COP CPU D/A, DAC EEPROM EPROM
The digits following the `$' are in hexadecimal format. The digits following the `%' are in binary format. Analog-to-digital (converter). In this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. Eight bits. Condition codes register; an integral part of the CPU. A ceramic package type, principally used for EPROM and high temperature devices. `0' -- the logic zero state; the opposite of `set'. Complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Computer operating properly. aka `watchdog'. This circuit is used to detect device runaway and provide a means for restoring correct operation. Central processing unit. Digital-to-analog (converter). Electrically erasable programmable read only memory. aka `EEROM'. Erasable programmable read only memory. This type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka `PROM'. Electrostatic discharge. In this mode the internal address and data bus lines are connected to external pins. This enables the device to be used in much more complex systems, where there is a need for external memory for example.
ESD Expanded mode
TPG
MC68HC05L28
GLOSSARY
MOTOROLA i
EVS HCMOS I/O Input capture
Evaluation system. One of the range of platforms provided by Motorola for evaluation and emulation of their devices. High-density complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. Input/output; used to describe a bidirectional pin or function. (IC) This is a function provided by the timing system, whereby an external event is `captured' by storing the value of a counter at the instant the event is detected. This refers to an asynchronous external event and the handling of it by the MCU. The external event is detected by the MCU and causes a predetermined action to occur. Interrupt request. The overline indicates that this is an active-low signal format. A kilo-byte (of memory); 1024 bytes. Liquid crystal display. Least significant byte. Motorola's family of advanced 8-bit MCUs. Microcontroller unit. Motorola interconnect bus. A single wire, medium speed serial communications protocol. Most significant byte. Half a byte; four bits. Non-return to zero. The opcode is a byte which identifies the particular instruction and operating mode to the CPU. See also: prebyte, operand. The operand is a byte containing information the CPU needs to execute a particular instruction. There may be from 0 to 3 operands associated with an opcode. See also: opcode, prebyte. (OC) This is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a predefined value. Plastic leaded chip carrier package. Phase-locked loop circuit. This provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. This byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. See also: opcode, operand.
Interrupt
IRQ kbyte LCD LSB M68HC11 MCU MI BUS MSB Nibble NRZ Opcode Operand
Output compare
PLCC PLL
Prebyte
TPG
MOTOROLA ii
GLOSSARY
MC68HC05L28
Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or VDD. PWM Pulse width modulation. This term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. Quad flat pack package. Random access memory. Fast read and write, but contents are lost when the power is removed. Radio frequency interference. Real-time interrupt. Read-only memory. This type of memory is programmed during device manufacture and cannot subsequently be altered. A standard serial communications protocol. Successive approximation register. Serial communications interface. `1' -- the logic one state; the opposite of `clear'. An area in the central belt of Scotland, so called because of the concentration of semiconductor manufacturers and users found there. In this mode the device functions as a self contained unit, requiring only I/O devices to complete a system. Serial peripheral interface. This mode is intended for factory testing. Transistor-transistor logic. Universal asynchronous receiver transmitter. Voltage controlled oscillator.
QFP RAM RFI RTI ROM RS-232C SAR SCI Set Silicon glen Single chip mode SPI Test mode TTL UART VCO Watchdog Wired-OR Word XIRQ
see `COP'.
A means of connecting outputs together such that the resulting composite output state is the logical OR of the state of the individual outputs. Two bytes; 16 bits. Non-maskable interrupt request. The overline indicates that this has an active-low signal format.
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MC68HC05L28
GLOSSARY
MOTOROLA iii
THIS PAGE LEFT BLANK INTENTIONALLY
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MOTOROLA iv
GLOSSARY
MC68HC05L28
INDEX
In this index numeric entries are placed first; page references in italics indicate that the reference is to a figure.
56-pin SDIP mechanical dimensions 13-2 56-pin SDIP package 13-1, A-6
C
C-bit in CCR 11-3 CCR - condition code register 11-2 CH3 - CH0 bits in ADSTAT 9-4 clocks crystal 2-8 external clock 2-8 OSC1, OSC2 2-7 oscillator connections 2-7 CO1E bit in TCR1 6-5 CO2E bit in TCR2 6-6 COCO bit in ADSTAT 9-3 COND -- port D control register 4-4 COP watchdog 10-2 reset times 5-3 COPON bit in OPT 1-3 core timer block diagram 5-1 during STOP mode 5-5 during WAIT mode 5-5 interrupts 10-7 counter 6-3 registers 6-3 CPEN bit in EEPROG 3-3 CPU A - accumulator 11-1 addressing modes 11-11-11-13 CCR - condition code register 11-2 instruction set 11-3-11-10 PC - program counter 11-2 programming model 11-1 SP - stack pointer 11-2 stacking order 11-2 X - index register 11-2 crystal 2-8 CTCR -- core timer counter register 5-5 CTCSR -- core timer control/status register CTOF - core timer overflow 5-3 CTOFE - core timer overflow enable 5-4 RT1, RT0 - real time interrupt rate select 5-4 RTIE - real time interrupt enable 5-4 RTIF - real time interrupt flag 5-4
A
A - accumulator 11-1 A/D converter block diagram 9-2 pins 2-9 ACH, ACL -- alternate counter registers 6-3 AD0 - AD1 2-9 ADDATA -- A/D result data register 9-5 addressing modes 11-11-11-13 ADIN -- A/D input register 9-5 ADON bit in ADSTAT 9-3 ADR7 - ADR1 bits in MADR 8-6 ADRC bit in ADSTAT 9-3 ADSTAT -- A/D status/control register ADON - A/D converter ON 9-3 ADRC - RC oscillator control 9-3 CH3 - CH0 - A/D channel bits 9-4 COCO - conversion complete flag 9-3 ADx analog input 9-6 alternate counter registers 6-3
B
bit set/clear addressing mode 11-13 bit test and branch addressing mode 11-13 block diagrams A/D converter 9-2 core timer 5-1 LCD 7-1 MC68HC05L28 1-2 MC68HC705L28 1-2 programmable timer 6-2 BP0 - BP3 2-9
TPG
MC68HC05L28
INDEX
MOTOROLA v
CTOF bit in CTCSR 5-3 CTOFE bit in CTCSR 5-4
D
data retention mode 2-12 data transfer 8-4 DDRA, DDRB, DDRD -- port data direction registers 4-3 direct addressing mode 11-11 DISON bit in LCD 7-8
E
EEPGM bit in EEPROG 3-4 EEPROM EEPROG -- programming register 3-3 CPEN - charge pump enable 3-3 EEPGM - program control 3-4 EERC - RC oscillator control 3-4 ER1, ER0 - erase select 3-3 LATCH - latch control 3-4 erase mode select 3-3 EERC bit in EEPROG 3-4 ELAT bit in PCR 3-5, A-5 EPROM bootloader mode 2-4, A-2 PCR -- programming register 3-5, A-5 ER1, ER0 bits in EEPROG 3-3 erase mode select 3-3 extended addressing mode 11-12 external clock 2-8
F
FDISP bit in LCD 7-8 flowcharts interrupt 10-4 STOP mode 2-11 WAIT mode 2-13 FP0 - FP17 2-9
H
H-bit in CCR 11-3
I
I/O ports -- see ports I2C-bus 8-4 arbitration 8-4 clock synchronization 8-5 configuration 8-2 handshaking 8-5 interrupts 10-8
MADR -- I2C-bus address register 8-6 MCR -- I2C-bus control register 8-7 MDR -- I2C-bus data register 8-10 MFDR -- I2C-bus frequency divider register 8-6 MSR -- I2C-bus status register 8-8 programming considerations 8-10 protocol 8-2 repeated START signal 8-4 SCL 8-2, 8-5 SDA 8-2 slave address transmission 8-2 START signal 8-2 STOP signal 8-4 I-bit in CCR 11-3 IC1F bit in TSR 6-7 IC1IE bit in TCR1 6-4 IC2F bit in TSR 6-7 IC2IE bit in TCR1 6-4 ICH1, ICL1 -- input capture register 1 6-9 ICH2, ICL2 -- input capture register 2 6-10 IEDG1 bit in TCR1 6-5 IEDG2 bit in TCR1 6-5 immediate addressing mode 11-11 indexed addressing modes 11-12 inherent addressing mode 11-11 input capture 6-9 instruction set 11-3-11-10 tables of instructions 11-5-11-10 interrupts core timer 10-7 external 10-5 flowchart 10-4 I2C-bus 10-8 maskable 10-3 non-maskable 10-3 priorities 10-3 programmable timer 10-7 RTI 5-2 SWI 10-3 IRQ0 10-5 IRQ0, IRQ1, IRQ2 2-6 IRQ1 status/control register IRQ1ENA - IRQ1 interrupt enable 10-5 IRQ1INT - IRQ1 interrupt flag 10-5 IRQ1LV, IRQ1EDG - IRQ1 interrupt sensitivity 10-5 IRQ1RST - IRQ1 interrupt flag reset bit 10-6 IRQ1VAL - IRQ1 pin status 10-6 IRQ2 status/control register IRQ2ENA - IRQ2 interrupt enable 10-6 IRQ2INT - IRQ2 interrupt flag 10-6 IRQ2LV, IRQ2EDG - IRQ2 interrupt sensitivity 10-6 IRQ2RST - IRQ2 interrupt flag reset bit 10-7 IRQ2VAL - IRQ2 pin status 10-7 IRQED bit in OPT 1-3
J
junction temperature 12-2
TPG
MOTOROLA vi
INDEX
MC68HC05L28
L
LATCH bit in EEPROG 3-4 LCD block diagram 7-1 during WAIT mode 7-8 pins 2-9 RAM 3-1, 7-2 timing diagrams 7-3-7-7 timing signals 7-3 voltage level selection 7-3 LCD -- LCD control register DISON - LCD display ON/OFF 7-8 FDISP - LCD display frequency 7-8 MUX4, MUX3 - LCD multiplex ratio 7-8 VLCDON - LCD voltage select 7-8 low power modes data retention 2-12 STOP 2-10 WAIT 2-12
MSR -- I2C-bus status register 8-8 MSTA bit in MCR 8-8 MTX bit in MCR 8-8 MUX4, MUX3 bits in LCD 7-8
N
N-bit in CCR 11-3
O
OC1F bit in TSR 6-7 OC1IE bit in TCR1 6-4 OC2F bit in TSR 6-8 OC2IE bit in TCR2 6-6 OCH1, OCL1 -- output compare register 1 6-11 OCH2, OCL2 -- output compare register 2 6-12 OLVL1 bit in TCR1 6-5 OLVL2 bit in TCR2 6-6 operating modes -- see modes of operation OPT -- option register 1-3 COPON - COP enable/disable bit in OPT 1-3 IRQED - IRQ edge sensitivity bit in OPT 1-3 order numbers 14-1 order numbers (MC68HC705L28) A-6 OSC1, OSC2 2-7 oscillator -- see clocks oscillator connections 2-7 output compare 6-11
M
MAAS bit in MSR 8-8 MADR -- I2C-bus address register 8-6 MAL bit in MAL 8-9 mask options 1-3 MBB bit in MSR 8-9 MBC4 - MBC0 bits in MFDR 8-6 MC68HC05L28 block diagram 1-2 mask options 1-3 modes of operation 2-2 MC68HC705L28 block diagram 1-2 mask options 1-3 modes of operation 2-4 MCF bit in MSR 8-8 MCR -- I2C-bus control register 8-7 MDR -- I2C-bus data register 8-10 memory EEPROM 3-3 LCD RAM 3-1 memory map 3-2 RAM 3-1 register outline 3-6 MEN bit in MCR 8-7 MFDR -- I2C-bus frequency divider register 8-6 MIEN bit in MCR 8-7 MIF bit in MSR 8-9 modes of operation data retention 2-12 entry conditions 2-1 EPROM bootloader 2-4, A-2 RAM bootloader (MC68HC05L28) 2-2 RAM bootloader (MC68HC705L28) A-4 single chip 2-2 STOP 2-10 WAIT 2-12
P
PA0 - PA7, PB0 - PB7 2-9 packages 56-pin SDIP 13-1, A-6 mechanical dimensions 13-2 PC - program counter 11-2 PCR -- programming register ELAT - EPROM latch control 3-5, A-5 PGM - EPROM program control 3-5, A-5 PD0 - PD5 2-9 PGM bit in PCR 3-5, A-5 pins AD0 - AD1 2-9 BP0 - BP3, FP0 - FP17 2-9 IRQ0, IRQ1, IRQ2 2-6 OSC1, OSC2 2-7 PA0 - PA7, PB0 - PB7 2-9 PD0 - PD5 2-9 RESET 2-8 VDD, VSS 2-6 VPP6 A-4 VREFH, VREFL 2-9 port pins 2-9 PORTA, PORTB, PORTD -- port data registers 4-3
TPG
MC68HC05L28
INDEX
MOTOROLA vii
ports data direction registers 4-3 I/O programming 4-1 pin states 4-1 port D 4-2 port D configuration 4-4 port D control register 4-4 port D select register 4-4 port data registers 4-3 port structure 4-2 ports A and B 4-2 registers 4-3 power-on reset 10-1 programmable timer block diagram 6-2 counter 6-3 during STOP mode 6-13 during WAIT mode 6-13 input capture register 1 6-9 input capture register 2 6-10 interrupts 10-7 output compare register 1 6-11 output compare register 2 6-12 timer state diagrams 6-13
TCAP2 - timer capture 2 select 4-5 TCMP1 - timer compare 1 select 4-5 TCMP2 - timer compare 2 select 4-5 SELD -- port D select register 4-4 single chip mode 2-2 SP - stack pointer 11-2 SRW bit in MSR 8-9 STOP mode 2-10 flowchart 2-11
T
TCAP1 bit in TSR 6-8 TCAP1 select bit in SELD 4-5 TCAP2 bit in TSR 6-8 TCAP2 select bit in SELD 4-5 TCH, TCL -- counter registers 6-3 TCMP1 select bit in SELD 4-5 TCMP2 select bit in SELD 4-5 TCR1 -- timer control register 1 CO1E - timer compare 1 output enable 6-5 IC1IE - input capture 1 interrupt enable 6-4 IC2IE - input capture 2 interrupt enable 6-4 IEDG1 - input edge 1 6-5 IEDG2 - input edge 2 6-5 OC1IE - output compare 1 interrupt enable 6-4 OLVL1 - input edge 1 6-5 TOIE - timer overflow interrupt enable 6-5 TCR2 -- timer control register 2 CO2E - output level 2 6-6 OC2IE - output compare 2 interrupt enable 6-6 OLVL2 - input edge 2 6-6 TOF bit in TSR 6-7 TOIE bit in TCR1 6-5 TRXD7 - TDR0 bits in MSR 8-10 TSR -- timer status register IC1F - input capture 1 flag 6-7 IC2F - input capture 2 flag 6-7 OC1F - output compare 1 flag 6-7 OC2F - output compare 2 6-8 TCAP1 - timer capture 1 6-8 TCAP2 - timer capture 2 6-8 TOF - timer overflow flag 6-7 TXAK bit in MCR 8-8
R
RAM 3-1 RAM (LCD) 3-1 RAM bootloader mode (MC68HC05L28) 2-2 RAM bootloader mode (MC68HC705L28) A-4 real time interrupts 5-2 register outline 3-6 relative addressing mode 11-13 RESET 2-8 resets COP 10-2 power-on 10-1 RESET pin 10-1 RT1, RT0 bits in CTCSR 5-4 RTI real time interrupts 5-2 RTIE bit in CTCSR 5-4 RTIF bit in CTCSR 5-4 RVU - ROM verification units 14-2 RXAK bit in MSR 8-9
V S
SCL 8-2, 8-5 SCL0 select bit in SELD 4-4 SDA 8-2 SDA0 select bit in SELD 4-4 SELD SCL0 - I2C clock select 4-4 SDA0 - I2C data select 4-4 TCAP1 - timer capture 1 select 4-5 VDD, VSS 2-6 VLCDON bit in LCD 7-8 VPP6 A-4 VREFH, VREFL 2-9
W
WAIT mode 2-12 flowchart 2-13
TPG
MOTOROLA viii
INDEX
MC68HC05L28
X
X - index register 11-2
Z
Z-bit in CCR 11-3
TPG
MC68HC05L28
INDEX
MOTOROLA ix
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TPG
MOTOROLA x
INDEX
MC68HC05L28
CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D)
Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. Excellent Organization Readability Understandability Accuracy Illustrations Comments: Poor Excellent Tables Table of contents Index Page size/binding Overall impression Poor
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INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE I2C-BUS A/D CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION
TPG MC68HC705L28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 A
INTRODUCTION MODES OF OPERATION AND PIN DESCRIPTIONS MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE I2C-BUS A/D CONVERTER RESETS AND INTERRUPTS CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL DATA ORDERING INFORMATION MC68HC705L28
TPG
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1 2 3 4 5 6 7 8 9 10 11 12 13 14
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